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Compal confidential
2
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Schematics Document Mobile Dothan uFCPGA with Intel Alviso_GM+ICH6-M core logic 2005-02-15 3
3
LA-2592 REV:0.3
4
4
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
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Compal Electronics, Inc. Cover Sheet
Size Document Number Custom LA-2592 Date:
Rev 0.3 Sheet
Monday, February 21, 2005 E
1
of
46
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B
C
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Compal confidential File Name : LA-2592 VRAM 128MByte (32MByte*4)
1
1
Mobile Dothan/Yonah uFCPGA-478 CPU
Fan Control page 15
DDR300/300
page 4,5,6
M/B-NV44M VGA/B CONN LS-2597
FSB
H_A#(3..31)
PCI-E
400/533MHz
Intel Alviso GMCH PCBGA 1257
page 16
2
page 15
DDR1 -333
M/B-S/B CONN LS-2594
DDR BANK0 32M*16*4 DDR-SO-DIMM1 page 12,13,14
One Channel
page 7,8,9,10,11
M/B-S/B CONN LS-2594 Camera/BlueTooth page 17 conn M/B-S/B CONN LS-2595 USB conn x2
USB2.0
PCI-E(DMI)
TV-OUT / CRT page 17 conn
page 18
H_D#(0..63)
page 16
LVDS CONN
Clock Generator ICS 954226
Thermal Sensor ADM1031AR
USB2.0
2
page 32
USB conn x2
page 32
PCI BUS
Intel ICH6-M Gigabit LAN RTL8110SBL/ 8100CLpage 24
Mini PCI socket page 28
IEEE1394 TSB43AB21
CardBus Controller page 25
3
RJ45/11 CONN M/B-S/B CONN page 24 LS-2595
Slot 0 page 26
AC-LINK
page 29
IDEBUS
4in1 Slot page 25
page 32
EC KB910L page 33
RTC CKT. page 19
M/B-S/B CONN LS-2593
page 34
Int.KBD page 33
Flash ROM SST39VF080-70
Touch Pad CONN.
4
page 32
DC/DC Interface CKT.
page 34
page 35
IDE HDD Connector page
23
AMP & Audio Jack APA2121 page 31
IDE ODD Connector page
23
SubBoard CONN List: LS-2597 VGA/B conn LS-2592 SWDJ/B conn LS-2593 TP/B conn LS-2594 CRT/TV-OUT conn LS-2595 USB&1394/B conn
LS-2594 CRT/TV-OUT List: CRT conn * 1 TV-OUT conn * 1 USB conn * 2 BlueTooth conn * 1 Num LED * 1 CAP LED * 1 Scroll LED * 1 Lid Switch * 1
Intel CPU debug conn EC debug conn SW debug conn Switch Button list: Power Botton(Sub/B) Lid Switch LED Function list: AC Power LED Charge LED HDD LED
LS-2595 USB&1394/B List: USB conn* 2 1395 conn * 1
Power Circuit DC/DC
Title
36,37,38,39,40,41,42
A
3
LS-2592 SWDJ/B List: SWDJ switch Button * 5 WL/BT on/foff Button *1 WL/BT LED *1
LPC BUS
1394 conn
Power On/Off CKT.
Audio CKT ALC250-VC
page 19,20,21,22
CB-714
page 27
mBGA-609
MO DEM AGERE CPS1038 page 30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
C
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Page 34 Page 34 4
Page 32 Page 32 Page 32
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
Page 32 Page 32 Page 32 Page 17 Page 32 Page 4 Page 33 Page 33
Block Diagram Sheet
Tuesday, February 15, 2005 E
Rev 0.3 2
of
46
5
4
3
2
1
I2C / SMBUS ADDRESSING External PCI Devices
D
DEVICE
IDSEL #
L AN
AD17
REQ/GNT # 0
PIRQ F
CARD BUS
AD20
1
A
1394
AD16
2
E
Wireless LAN(MINI PCI)
AD18
3
G,H
D
B
Cardreader
Power Managment table
+CPU_CORE +VCCP(1.05V) +5VS +3VS +2.5VS +1.5VS +1.25VS +1.1VS(VGA/B) +1.2VS(VGA/B) +1.8VS(VGA/B)
Signal
C
State
+12VALW +3VALW +5VALW
+3V +2.5V
S0
ON
ON
ON
S1
ON
ON
ON
S3
ON
ON
OFF
S5 S4/AC
ON
OFF
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
C
B
B
SMBUS Control Table SOURCE
SMB_EC_CK1 SMB_EC_DA1
KB910L
SMB_EC_CK2 SMB_EC_DA2
KB910L
ICH_SMBCLK ICH_SMBDATA
A
INVERTER
BATT
SERIAL EEPROM
THERMAL SENSOR (CPU) ADM1032
SODIMM
CLK CHIP
MINI PCI
LCD
ICH6-M
LCD_DDCCLK LCD_DDCDATA
Alviso GM-GP
I2CC_SCL I2CC_SDA
NV44M A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
Design Note Sheet
Tuesday, February 15, 2005 1
Rev 0.1 3
of
46
5
4
3
2
1
ZZZ1
LA-25 92 REV 0.3
18 18
CLK_ITP CLK_ITP#
H_ADSTB#0 H_ADSTB#1
DINV0# DINV1# DINV2# DINV3#
D25 J26 T24 AD20
DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3#
C23 K24 W25 AE24 C22 L24 W24 AE25
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
A20M# FERR# IGNNE# INIT# LINT0 LINT1
C2 D3 A3 B5 D1 D4
H_A20M# H_FERR# H_IGNNE# H_INIT# H_INTR H_NMI
STPCLK# SMI#
C6 B4
H_STPCLK# H_SMI#
REQ0# REQ1# REQ2# REQ3# REQ4#
U3 AE5
ADSTB0# ADSTB1#
A16 A15
ITP_CLK0 ITP_CLK1
B15 B14
BCLK0 BCLK1
N2 L1 J3 N4 L4 H2 K3 K4 A4 J2 B11
ADS# BNR# BPRI# BR0# DEFER# DRDY# HIT# HITM# IERR# LOCK# RESET#
C
CLK_CPU_BCLK CLK_CPU_BCLK#
18 CLK_CPU_BCLK 18 CLK_CPU_BCLK#
+VCCP
R37 1 2 56_0402_5%
7
7 7 7 7 7 7 7 7
H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRDY# H_HIT# H_HITM#
7 7
H_LOCK# H_RESET#
H_ADS# H_BNR# H_BPRI# H_BR0# H_DEFER# H_DRD Y# H_HIT# H_HITM# H_IERR# H_LOCK# H_RESET#
1" ~ 6.5"
H_RS#[0..2]
7
H_RS#0 H_RS#1 H_RS#2 H_TRDY#
H_TRDY#
ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3
B
H_DPRSLP will change to H_DPRSTP in future collateral version.
7 20 20 7
ITP_DBRESET# H_DBSY# H_DPSLP# H_DPRSLP#
H_DBSY# H_DPSLP# H_DPRSLP# H_DPWR#
ITP_BPM#4 ITP_BPM#5 H_PROCHOT#
20 H_PWRGOOD 7,20 H_CPUSLP#
H_CPUSLP# ITP_TCK ITP_TDI ITP_TDO TEST1 TEST2 ITP_TMS ITP_TRST# H_THERMDA H_THERMDC
15 H_THERMDA 15 H_THERMDC 7,20 H_THERMTRIP#
H1 K1 L2 M3
C8 B8 A9 C9
HOST CLK
CONTROL GROUP
RS0# RS1# RS2# TRDY#
BPM0# BPM1# BPM2# BPM3#
Place near JITP 1" ITP_TDO 2 54.9_0402_1% Place near JITP 0.5" H_RESET# 2 54.9_0402_1% ITP_BPM#5 2 56_0402_5%
1
Place near JITP 0.5" R38 21 ITP_DBRESET#
ITP_DBRESET#2 1 @ 200_0402_5% ITP_BPM#0 ITP_BPM#1 ITP_BPM#2
ITP_BPM#[0:3] < 6" Spacing 1:2 ITP_BPM#3 ITP_BPM#4 R46 @ 22.6_0402_1% H_RESET# 1 2
ITP_BPM#5 RESETITP#
Place near JITP 0.5" R47 @ 22.6_0402_1% ITP_TDO 1 2
CLK_ITP CLK_ITP# ITP_TDO_R
Spacing 8 mil
ITP_TCK ITP_TRST# ITP_TMS ITP_TDI
PAD
T1
PAD
T6
PAD
T5
PAD
T8
PAD
T2
PAD
T9
PAD PAD
T3 T15
PAD PAD PAD
T18 T19 T16
PAD PAD PAD PAD
T17 T14 T4 T13
R48 R33
+VCCP
1 1
A7 M2 B7 G1 C19 A10 B10 B17
DBR# DBSY# DPSLP# DPRSTP# DPWR# PRDY# PREQ# PROCHOT#
E4 A6 A13 C12 A12 C5 F23 C11 B13
PWRGOOD SLP# TCK TDI TDO TEST1 TEST2 TMS TRST#
B18 A18 C17
THERMDA DIODE THERMDC THERMTRIP#
MISC
THERMAL
D
39.2 R42 39.2_0603_1% ITP_TMS 1 2 Within 2" of the CPU R179150_0402_5% ITP_TDI 1 2 Within 2" of the CPU R177680_0402_5% ITP_TRST# 1 2 Within 2" of the CPU R50 27.4_0402_1% ITP_TCK 1 2 Within 2" of the CPU
C
+3VS +VCCP R258 1K_0402_5%
R266 56_0402_5% PROCHOT# 33 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
7 7 7 7
R253 56_0402_5%
C
Q29 2SC2411K_SC59
2 B E
3
CLK_ITP CLK_ITP#
R49
1
H_ADSTB#0 H_ADSTB#1
DATA GROUP
+VCCP
Check ITP signal for Dothan
2
7 7
R2 P3 T2 P1 T1
A19 A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 H23 G25 L23 M26 H24 F25 G24 J23 M23 J25 L26 N24 M25 H26 N25 K25 Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 U26 V24 U25 V26 Y23 AA26 Y25 AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 AF26
Dothan
ADDR GROUP
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#
1
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31#
1
H_REQ#[0..4]
P4 U4 V3 R3 V2 W1 T4 W2 Y4 Y1 U1 AA3 Y3 AA2 AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1
2
LA2591 Rev0.1-DA600001600(6 layer) LA2592 Rev0.3-DA800005000(8 layer)
7
H_D#[0..63] 7
U15A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
1
D
H_A#[3..31]
LEGACY CPU
H_DSTBN#[0..3] 7
B
2
7
H_PROCHOT# H_DSTBP#[0..3] 7
H_A20M# 20 H_FERR# 20 H_IGNNE# 20 H_INIT# 20 H_INTR 20 H_NMI 20 H_STPCLK# 20 H_SMI# 20
+VCCP
R32 200_0402_5% 1 2 H_PW RGOOD
Add pullups for PWRGOOD and THERMTRIP per INTEL
TYCO_1612365-1_Dothan
R251 A
TEST2
TEST1
1
A
2
@ 1K_0402_5% R35 1 2 @ 1K_0402_5% Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
Dothan Processor(1/2) Sheet
Tuesday, February 15, 2005 1
4
of
Rev 0.1 46
5
4
3
2
1
+CPU_CORE U15C
+1.5VS
U15B VCCSENSE VSSSENSE
VCCA0 VCCA1 VCCA2 VCCA3
P23 W4
VCCQ0 VCCQ1
D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L5 L21 M6 M22 N5 N21 P6 P22 R5 R21 T6 T22 U21
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
D6 D8 D18 D20 D22 E5 E7 E9 E17 E19 E21 F6 F8 F18
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
PSI#
E1
PSI#
VID0 VID1 VID2 VID3 VID4 VID5
E2 F2 F3 G3 G4 H4
VID0 VID1 VID2 VID3 VID4 VID5
+VCCP
1
1
2
2
C341 10U_1206_6.3V6M
C
+CPU_CORE
42
PSI#
+VCCP 1
Spacing
VID0 VID1 VID2 VID3 VID4 VID5
Dothan
2
Spacing 25mil
Layout Note:
1
500 mil max length Spacing 25mil R247 2K_0402_1%
AD26
+V_CPU_GTLREF
18 18
CPU_BSEL0 CPU_BSEL1
20 mils
1
1
Resistor placed within 0.5" of CPU pin.Trace
T10 T7 T20 T12 T11
R250 R41 R40 should be at least 25 54.9_0402_1% 27.4_0402_1% 54.9_0402_1%miles away from any 2
2
R249 27.4_0402_1%
2
1
2
5 mils (55 Ohm) 20 mils(27.4Ohm) 5 mils(55 Ohm) 1
B
Layout close CPU
2
R248 1K_0402_1%
+V_CPU_GTLREF
42 42 42 1:2 42 42 42
VCCSENSE VSSSENSE
F26 B1 N1 AC26
D
C340 0.01U_0603_16V7K
AE7 AF6
POWER, GROUNG, RESERVED SIGNALS AND NC
R181 @ 54.9_0402_1% 1 2 1 2 R178 @ 54.9_0402_1%
other toggling signal.
PAD PAD PAD PAD PAD
GTLREF
CPU_BSEL0 CPU_BSEL1
C16 C14
BSEL0 BSEL1
COMP0 COMP1 COMP2 COMP3
P25 P26 AB2 AB1
COMP0 COMP1 COMP2 COMP3
B2 C3 E26 AF7 AC1
RSVD RSVD RSVD RSVD RSVD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
A2 A5 A8 A11 A14 A17 A20 A23 A26 B3 B6 B9 B12 B16 B19 B22 B25 C1 C4 C7 C10 C13 C15 C18 C21 C24 D2 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6 J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1
F20 F22 G5 G21 H6 H22 J5 J21 K22 U5 V6 V22 W5 W21 Y6 Y22 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC9 AC11 AC13 AC15 AC17 AC19 AD8 AD10 AD12 AD14 AD16 AD18 AE9 AE11 AE13 AE15 AE17 AE19 AF8 AF10 AF12 AF14 AF16 AF18
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 R4 R6 R22 R25 T3 T5 T21 T23
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Dothan
POWER, GROUND
T26 U2 U6 U22 U24 V1 V4 V5 V21 V25 W3 W6 W22 W23 W26 Y2 Y5 Y21 Y24 AA1 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB26 AC2 AC5 AC8 AC10 AC12 AC14 AC16 AC18 AC21 AC24 AD1 AD4 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD22 AD25 AE3 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE23 AE26 AF2 AF5 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF24
D
C
B
TYCO_1612365-1_Dothan TYCO_1612365-1_Dothan
A
A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
Dothan Processor(2/2) Sheet
Tuesday, February 15, 2005 1
5
of
Rev 0.1 46
5
4
3
+CPU_CORE
1
+CPU_CORE
1
1 C84 10U_1206_6.3V6M
2
2
2
1 C87 10U_1206_6.3V6M
2
1 C90 10U_1206_6.3V6M
2
1 C93 10U_1206_6.3V6M
2
1 C97 10U_1206_6.3V6M
2
1 C99 10U_1206_6.3V6M
2
1 C83 10U_1206_6.3V6M
2
1 C86 10U_1206_6.3V6M
2
1 C89 10U_1206_6.3V6M
2
C92 10U_1206_6.3V6M
D
D
+CPU_CORE
+CPU_CORE
1
1 C259 10U_1206_6.3V6M
2
2
1 C265 10U_1206_6.3V6M
2
1 C81 10U_1206_6.3V6M
2
1 C82 10U_1206_6.3V6M
2
1 C100 10U_1206_6.3V6M
2
+CPU_CORE
2
1 C102 10U_1206_6.3V6M
2
1 C98 10U_1206_6.3V6M
2
1 C260 10U_1206_6.3V6M
2
C267 10U_1206_6.3V6M
+CPU_CORE
1
1 C274 10U_1206_6.3V6M
2
1 C101 10U_1206_6.3V6M
2
1 C280 10U_1206_6.3V6M
2
1 C293 10U_1206_6.3V6M
2
1 C301 10U_1206_6.3V6M
2
1 C273 10U_1206_6.3V6M
2
1 C279 10U_1206_6.3V6M
2
1 C292 10U_1206_6.3V6M
2
1 C300 10U_1206_6.3V6M
2
1 C257 10U_1206_6.3V6M
2
C256 10U_1206_6.3V6M
+CPU_CORE
1
1 C303 10U_1206_6.3V6M
2
C
2
1 C302 10U_1206_6.3V6M
2
1 C282 10U_1206_6.3V6M
2
1 C283 10U_1206_6.3V6M
2
C272 10U_1206_6.3V6M C
Near VCORE regulator. +CPU_CORE
1 C94 B
330U_D2E_2.5VM
+
1 C286
1
+
C95
+
ESR <= 3m ohm
1 C285
+
330U_D2E_2.5VM 2 330U_D2E_2.5VM 2 2 2 @ 330U_D2E_2.5VM
Capacitor > 880 uF
B
+VCCP
1 +
C70 150U_D_6.3VM
2
1
2
1 C85 0.1U_0402_16V4Z
2
1 C88 0.1U_0402_16V4Z
2
1 C91 0.1U_0402_16V4Z
2
1 C96 0.1U_0402_16V4Z
2
1 C103 0.1U_0402_16V4Z
2
1 C104 0.1U_0402_16V4Z
1 C78 0.1U_0402_16V4Z
2
2
1 C80 0.1U_0402_16V4Z
2
1 C105 0.1U_0402_16V4Z
2
C79 0.1U_0402_16V4Z
A
A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
Dothan Bypass Sheet
Tuesday, February 15, 2005 1
Rev 0.1 6
of
46
5
B
4
F8 B5 G6 H_DRD Y# F7 H_DEFER# E6 TP_H_EDRDY# F6 H_HITM# D6 H_HIT# D4 H_LOCK# B3 H_BR0# E7 H_BNR# A5 H_BPRI# D5 H_DBSY# C6 H_CPUSLP# G8 H_RS#0 A4 H_RS#1 C5 H_RS#2 B4
HADS# HTRDY# HDPWR# HDRDY# HDEFER# HEDRDY# HHITM# HHIT# HLOCK# HBREQ0# HBNR# HBPRI# HDBSY# HCPUSLP# HRS0# HRS1# HRS2#
HVREF HXRCOMP HXSCOMP HYRCOMP HYSCOMP HXSWING HYSWING
H_VREF H_XRCOMP H_XSCOMP H_YRCOMP H_YSCOMP H_SWNG0 H_SWNG1
J11 C1 C2 T1 L1 D1 P1
+2.5V
ALVISO_BGA1257
PM-C0-SA0091501D0(R3)&SA0091501E0(R1) GM-B1-SA0091500A0(R3)&SA009150070(R1)
13 13
DDR_CLK3 DDR_CLK4
12 12
DDR_CLK0# DDR_CLK1#
13 13
DDR_CLK3# DDR_CLK4#
12
DDR_CKE0
13 13
DDR_CKE2 DDR_CKE3
12
DDR_SCS#0
13 13
DDR_SCS#2 DDR_SCS#3
+VCCP R174 10K_0402_1% +VCCP 12,13
1
2
SDREF
R172 10K_0402_1%
R157 80.6_0402_1%
DDR_CLK0 DDR_CLK1
AM33 AL1 AE11 AJ34 AF6 AC10
SM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK4 SM_CK5
AN33 AK1 AE10 AJ33 AF5 AD10
SM_CK0# SM_CK1# SM_CK2# SM_CK3# SM_CK4# SM_CK5#
AP21 AM21 AH21 AK21
SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3
AN16 AM14 AH15 AG16
SM_CS0# SM_CS1# SM_CS2# SM_CS3#
AF22 AF16 AP14 AL15 AM11 AN10
SM_OCDCOMP0 SM_OCDCOMP1 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3
AK10 AK11 AF37 AD1 AE27 AE28 AF9 AF10
SMRCOMPN SMRCOMPP SMVREF0 SMVREF1 SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT
DDR_CLK3# DDR_CLK4# DDR_CKE0 DDR_CKE2 DDR_CKE3 DDR_SCS#0 DDR_SCS#2 DDR_SCS#3
1
2
1
CFG/RSVD
2
CFG0 MCH_CLKSEL1 MCH_CLKSEL0 PAD T27 PAD T28
BM_BUSY# EXT_TS0# EXT_TS1# THRMTRIP# PWROK RSTIN#
DREF_CLKN DREF_CLKP DREF_SSCLKP DREF_SSCLKN NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11
J23 J21 H22 F5 AD30 AE29
PM_BMBUSY# 21
PM_EXTTS#0 PM_EXTTS#1
H_THERMTRIP# 4,20 +VCCP_PWRGD 33 PLTRST_MCH# 19,21,25,27
A24 A23 D37 C37
DREFCLK# 18 DREFCLK 18 SSC_DREFCLK 18 SSC_DREFCLK# 18
AP37 AN37 AP36 AP2 AP1 AN1 B1 A2 B37 A36 A37
R141 10K_0402_5% 2 1 R137 10K_0402_5% 2 1
PM_EXTTS#0
+2.5VS
CFG9
CFG[13:12]
R147 40.2_0402_1% 2 1
M_OCDOCMP0 M_OCDOCMP1
CFG16 (FSB Dynamic ODT) CFG18 (VCC Select) CFG19 (VTT Select)
@
+VCCP
Refer to sheet 19 for FSB frequency select
CFG0
3
R149
2
1
10K_0402_5%
Low = DMI x 2 High = DMI x 4
*
Low = DDR-II High = DDR-I
*
Low = DT/Transportable CPU High = Mobile CPU Low = Reverse Lane
*
High = Normal Operation 00 01 10 11
*
= Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation (Default)
*
Low = Disabled High = Enabled
*
Low = 1.05V (Default)
A
*
High = 1.5V Low = 1.05V (Default)
*
High = 1.2V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
D
C
Title
5
MCH_CLKSEL1 18 MCH_CLKSEL0 18
B
Layout Note: Rote as short as possible
@
SMRCOMPN SMRCOMPP SDREF
DMI
DMITXP0 DMITXP1 DMITXP2 DMITXP3
G16 H13 G14 F16 F15 G15 E16 D17 J16 D15 E15 D14 E14 H12 C14 H15 J15 H14 G22 G23 D23 G25 G24 J17 A31 A30 D26 D25
PM_EXTTS#1
CFG5
R168 221_0603_1% 2 1 2
Y33 AA37 AB33 AC37
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27
ALVISO_BGA1257
CFG[2:0]
R136 40.2_0402_1% 2 1
C247 0.1U_0402_16V4Z
1
R167 100_0402_1% 2 1
R173 221_0603_1% 2 1 2
R169 100_0402_1% 2 1
C253 0.1U_0402_16V4Z
1
+VCCP
H_SWNG1
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DDR_CLK0# DDR_CLK1#
R159 80.6_0402_1% 1 2
CFG7
H_SWNG0
DMITXN0 DMITXN1 DMITXN2 DMITXN3
+2.5V
CFG6
A
AA33 AB37 AC33 AD37
DDR_CLK3 DDR_CLK4
SDREF
10/20 mils
+VCCP
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
M_OCDOCMP0 M_OCDOCMP1
100mil
H_RS#[0..2]
DDR_CLK0 DDR_CLK1
DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3
DDR MUXING
12 12
Y31 AA35 AB31 AC35
CLK PM
HCPURST#
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
NC
H10
21 21 21 21
DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3
C252 0.1U_0402_16V4Z
H_ADS# H_TRDY# H_DPWR# H_DRDY# H_DEFER# T30 PAD 4 H_HITM# 4 H_HIT# 4 H_LOCK# 4 H_BR0# 4 H_BNR# 4 H_BPRI# 4 H_DBSY# 4,20 H_CPUSLP#
H_ADS# H_TRDY#
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
C22 0.1U_0402_16V4Z
4 4 4 4 4
H_RESET#
21 21 21 21
AA31 AB35 AC31 AD35
1
H_RESET#
HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 HDINV#0 HDINV#1 HDINV#2 HDINV#3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
2
4
HCLKN HCLKP
G4 K1 R3 V3 G5 K2 R2 W4 H8 K3 T7 U5
21 21 21 21
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
1
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
AB1 AB2
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
2
4 4 4 4
1
U5B 21 21 21 21
1
4 H_DSTBP#[0..3]
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
HPCREQ# HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HADSTB#0 HADSTB#1
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
E4 E1 F4 H7 E2 F1 E3 D3 K7 F2 J7 J8 H6 F3 K8 H5 H1 H2 K5 K6 J4 G3 H3 J1 L5 K4 J5 P7 L7 J3 P5 L3 U7 V6 R6 R5 P3 T8 R7 R8 U8 R4 T4 T5 R1 T3 V8 U6 W6 U3 V5 W8 W7 U2 U1 Y5 Y2 V4 Y7 W1 W3 Y3 Y6 W2
2
C
H_ADSTB#0 H_ADSTB#1
A11 A7 D7 B8 C7 A8 B9 E13
HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#
R160 R156 200_0402_1% 100_0402_1% 2 1 2 1
4 4
18 CLK_MCH_BCLK# 18 CLK_MCH_BCLK 4 H_DSTBN#[0..3]
TP_H_PCREQ# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADSTB#0 H_ADSTB#1
Alviso
C237 0.1U_0402_16V4Z
T29 PAD H_REQ#[0..4]
HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#
R163 54.9_0402_1% 2 1 R164 54.9_0402_1% 2 1
D
2
H_D#[0..63] 4
G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13
R165 24.9_0402_1% 2 1 R170 24.9_0402_1% 2 1
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 4
3
U5A
H_A#[3..31]
HOST
4
4
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
Alviso(1 of 5) Sheet
Tuesday, February 15, 2005 1
Rev 0.2 7
of
46
5
4
3
2
1
D
D
AK15 AK16 AL21
SA_BS0# SA_BS1# SA_BS2#
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
AJ37 AP35 AL29 AP24 AP9 AP4 AJ2 AD3
SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
AK36 AP33 AN29 AP23 AM8 AM4 AJ1 AE5
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7
AK35 AP34 AN30 AN23 AN8 AM5 AH1 AE4
SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13
AL17 AP17 AP18 AM17 AN18 AM18 AL19 AP20 AM19 AL20 AM16 AN20 AM20 AM15
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13
DDR_A_CAS# DDR_A_RAS# TP_MA_RCVENIN# TP_MA_RCVENOUT# DDR_A_WE#
AN15 AP16 AF29 AF28 AP15
SA_CAS# SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE#
C
12 DDR_A_MA[0..13]
12 DDR_A_CAS# 12 DDR_A_RAS# T21 PAD~D T22 PAD~D 12
DDR_A_WE#
DDR MEMORY SYSTEM A
12 DDR_A_DQS[0..7]
DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2
B
SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7 SADQ8 SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63
AG35 AH35 AL35 AL37 AH36 AJ35 AK37 AL34 AM36 AN35 AP32 AM31 AM34 AM35 AL32 AM32 AN31 AP31 AN28 AP28 AL30 AM30 AM28 AL28 AP27 AM27 AM23 AM22 AL23 AM24 AN22 AP22 AM9 AL9 AL6 AP7 AP11 AP10 AL7 AM7 AN5 AN6 AN3 AP3 AP6 AM6 AL4 AM3 AK2 AK3 AG2 AG1 AL3 AM2 AH3 AG3 AF3 AE3 AD6 AC4 AF2 AF1 AD4 AD5
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
U5D
DDR_A_D[0..63] 12 13 13 T24
DDR_B_BS#0 DDR_B_BS#1 PAD~D
DDR_B_BS#0 AJ15 DDR_B_BS#1 AG17 DDR_B_BS#2 AG21
This Symbol as same as Intel CRB schematic, So Layout Guide will show these signals routed differentially.
13 DDR_B_MA[0..13]
13 13 T25 PAD~D T26 PAD~D 13
DDR_B_CAS# DDR_B_RAS# DDR_B_WE#
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13
SB_BS0# SB_BS1# SB_BS2#
AF32 AK34 AK27 AK24 AJ10 AK5 AE7 AB7
SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7
AF34 AK32 AJ28 AK23 AM10 AH6 AF8 AB4
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7
AF35 AK33 AK28 AJ23 AL10 AH7 AF7 AB5
SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#
AH17 AK17 AH18 AJ18 AK18 AJ19 AK19 AH19 AJ20 AH20 AJ16 AG18 AG20 AG15
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13
DDR_B_CAS# AH14 DDR_B_RAS# AK14 TP_MB_RCVENIN# AF15 TP_MB_RCVENOUT# AF14 DDR_B_WE# AH16
DDR SYSTEM MEMORY B
U5C 12 DDR_A_BS#0 12 DDR_A_BS#1 T23 PAD~D 12 DDR_A_DM[0..7]
SB_CAS# SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE#
ALVISO_BGA1257
SBDQ0 SBDQ1 SBDQ2 SBDQ3 SBDQ4 SBDQ5 SBDQ6 SBDQ7 SBDQ8 SBDQ9 SBDQ10 SBDQ11 SBDQ12 SBDQ13 SBDQ14 SBDQ15 SBDQ16 SBDQ17 SBDQ18 SBDQ19 SBDQ20 SBDQ21 SBDQ22 SBDQ23 SBDQ24 SBDQ25 SBDQ26 SBDQ27 SBDQ28 SBDQ29 SBDQ30 SBDQ31 SBDQ32 SBDQ33 SBDQ34 SBDQ35 SBDQ36 SBDQ37 SBDQ38 SBDQ39 SBDQ40 SBDQ41 SBDQ42 SBDQ43 SBDQ44 SBDQ45 SBDQ46 SBDQ47 SBDQ48 SBDQ49 SBDQ50 SBDQ51 SBDQ52 SBDQ53 SBDQ54 SBDQ55 SBDQ56 SBDQ57 SBDQ58 SBDQ59 SBDQ60 SBDQ61 SBDQ62 SBDQ63
AE31 AE32 AG32 AG36 AE34 AE33 AF31 AF30 AH33 AH32 AK31 AG30 AG34 AG33 AH31 AJ31 AK30 AJ30 AH29 AH28 AK29 AH30 AH27 AG28 AF24 AG23 AJ22 AK22 AH24 AH23 AG22 AJ21 AG10 AG9 AG8 AH8 AH11 AH10 AJ9 AK9 AJ7 AK6 AJ4 AH5 AK8 AJ8 AJ5 AK4 AG5 AG4 AD8 AD9 AH4 AG6 AE8 AD7 AC5 AB8 AB6 AA8 AC8 AC7 AA4 AA5
C
B
ALVISO_BGA1257
A
A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
Alviso(2 of 5) Sheet
Tuesday, February 15, 2005 1
Rev 0.1 8
of
46
5
4
3
2
1
D
D
+1.5VS_PCIE
T46 PAD
A15 C16 A17 J18 B15 B16 B17
COMP/B Y/G C/R 1
17 17 17
H24 H25 AB29 AC29
R142
TVDAC_A TVDAC_B TVDAC_C TV_REFSET TV_IRTNA TV_IRTNB TV_IRTNC
17 17 17
CRT_BLU
17
CRT_GRN
17
CRT_RED 17 17
CLK_DDC2 DAT_DDC2
VSYNC HSYNC
CLK_DDC2 DAT_DDC2
E24 E23 E21 D21 C20 B20 A19 B19 H21 G21 J20
DDCCLK DDCDATA BLUE BLUE# GREEN GREEN# RED RED# VSYNC HSYNC REFSET
E25 F25 C23 C22 F23 F22 F26 C33 C31 F28 F27
LBKLT_CTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL
LVDS_ACLVDS_AC+
B30 B29 C25 C24
LACLKN LACLKP LBCLKN LBCLKP
LVDS_A0LVDS_A1LVDS_A2-
B34 B33 B32
LADATAN0 LADATAN1 LADATAN2
LVDS_A0+ LVDS_A1+ LVDS_A2+
A34 A33 B31
LADATAP0 LADATAP1 LADATAP2
C29 D28 C27
LBDATAN0 LBDATAN1 LBDATAN2
C28 D27 C26
LBDATAP0 LBDATAP1 LBDATAP2
1 2 R143 NONVGA@ 255_0402_1%
16 16 1 1
LCD_CLK 2 R133 2.2K_0402_5% LCD_DAT 2 R140 2.2K_0402_5%
16 16 16 2
BIA BK_EN LCD_CLK LCD_DAT EN_LCDVDD 1
BIA BK_EN LCD_CLK LCD_DAT EN_LCDVDD
R128 1.5K_0402_1% B
16 16
LVDS_ACLVDS_AC+
16 16 16
LVDS_A0LVDS_A1LVDS_A2-
16 16 16
LVDS_A0+ LVDS_A1+ LVDS_A2+
LVDS
+2.5VS
PCI - EXPRESS GRAPHICS
C
VGA
2
4.99K_0603_1%
SDVOCTRL_DATA SDVOCTRL_CLK GCLKN GCLKP
TV
T45 PAD 18 CLK_MCH_3GPLL# 18 CLK_MCH_3GPLL
MISC
U5G EXP_COMPI EXP_ICOMPO
D36 D34
PEGCOMP
EXP_RXN0/SDVO_TVCLKIN# EXP_RXN1/SDVO_INT# EXP_RXN2/SDVO_FLDSTALL# EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15
E30 F34 G30 H34 J30 K34 L30 M34 N30 P34 R30 T34 U30 V34 W30 Y34
PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15
EXP_RXP0/SDVO_TVCLKIN EXP_RXP1/SDVO_INT EXP_RXP2/SDVO_FLDSTALL EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15
D30 E34 F30 G34 H30 J34 K30 L34 M30 N34 P30 R34 T30 U34 V30 W34
PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15
EXP_TXN0/SDVOB_RED# EXP_TXN1/SDVOB_GREEN# EXP_TXN2/SDVOB_BLUE# EXP_TXN3/SDVOB_CLKN EXP_TXN4/SDVOC_RED# EXP_TXN5/SDVOC_GREEN# EXP_TXN6/SDVOC_BLUE# EXP_TXN7/SDVOC_CLKN EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15
E32 F36 G32 H36 J32 K36 L32 M36 N32 P36 R32 T36 U32 V36 W32 Y36
PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15
EXP_TXP0/SDVOB_RED EXP_TXP1/SDVOB_GREEN EXP_TXP2/SDVOB_BLUE EXP_TXP3/SDVOB_CLKP EXP_TXP4/SDVOC_RED EXP_TXP5/SDVOC_GREEN EXP_TXP6/SDVOC_BLUE EXP_TXP7/SDVOC_CLKP EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15
D32 E36 F32 G36 H32 J36 K32 L36 M32 N36 P32 R36 T32 U36 V32 W36
PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15
R125 24.9_0402_1% 1 2 PEG_RXN[0..15]
PEG_RXN[0..15] 16
C
PEG_RXP[0..15]
PEG_RXP[0..15] 16
This Symbol as same as Intel CRB schematic, So Layout Guide will show these signals routed differentially.
PEG_TXN[0..15]
PEG_TXN[0..15] 16
B
PEG_TXP[0..15]
PEG_TXP[0..15] 16
ALVISO_BGA1257 A
A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
Alviso(3 of 5) Sheet
Tuesday, February 15, 2005 1
Rev 0.2 9
of
46
2
1
2
1
2
+ 2
+1.5VS +1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_HPLL +1.5VS_MPLL
VCCA_SM0 VCCA_SM1 VCCA_SM2 VCCA_SM3
AF20 AP19 AF19 AF18
VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6
AE37 W37 U37 R37 N37 L37 J37
VCCA_3GPLL0 VCCA_3GPLL1 VCCA_3GPLL2
Y29 Y28 Y27
VCCA_3GBG VSSA_3GBG
F37 G37
VCC_SYNC
H20
VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC
V2.5_DDR_CAP6 V2.5_DDR_CAP4 V2.5_DDR_CAP3
ALVISO_BGA1257
ALVISO_BGA1257
2
1
2
0.1U_0402_16V4Z
1
C198 0.1U_0402_16V4Z
2
C199 0.1U_0402_16V4Z
2
2
1
2
C548 0.1U_0402_16V4Z
+1.5VS_PCIE
+ 2
1
2
1
2
+1.5VS_3GPLL 1
2
1
+2.5VS_CRT_DAC
2
2
+2.5VS 1
1 2 CHB1608U301_0603 +
1
2 C220 1 0.022U_0402_16V7K
2
2
+1.5VS
+1.5VS R13 L3 0.5_0805_1% BLM18PG600SN1_0603 1 23GRLL_R 2 1
1
2
2
+1.5VS
L1 BLM18PG330SN1_2P 2 1
+2.5VS_3GBG L2 CHB1608U301_0603 2 1 1 L21
2
L7 BLM18PG600SN1_0603 2 1
+
1
2
C195 0.1U_0402_16V4Z
1
2
2
1
1
1
1
2
2 C
2
+2.5VS
C20 0.1U_0402_16V4Z
1
2
C19 0.1U_0402_16V4Z
C443 @150U_D_6.3VM
Route VSSA3GBG gnd from GMCH to decoupling cap ground lead and then connect to the gnd plane.
B
1
1
1
1
1
C542 C543 C544 C545 C546 2 2 2 2 2
Route VSSACRTDAC gnd from GMCH to decoupling cap ground lead and then connect to the gnd plane.
+ 2
1
2
1 + 2
C242 0.1U_0402_16V4Z
1
+1.5VS_MPLL L8 CHB1608U301_0603 1 2
+1.5VS
C255 330U_D2E_2.5VM
+1.5VS_HPLL L9 CHB1608U301_0603 1 2 C250 330U_D2E_2.5VM
2
2
1
1
2
1
10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_6.3V6M 0.1U_0402_16V4Z
C73
2
1
0.1U_0402_16V4Z
C188
+
C186 330U_D2E_2.5VM
1
2
1
C234 0.1U_0402_16V4Z
+1.5VS_DPLLB L5 CHB1608U301_0603 1 2 +1.5VS
2
1
0.1U_0402_16V4Z
+1.5VS
2
C230
2
1
0.1U_0402_16V4Z
C205
+
C209 330U_D2E_2.5VM
1
+VCCP 1
C235 0.1U_0402_16V4Z
+1.5VS
C211 0.1U_0402_16V4Z
B
1
2
1
2
CRTDAC: Route caps within 250mil of Alviso. Route FB within 3" of Alviso.
+2.5V +1.5VS_DPLLA L6 CHB1608U301_0603 1 2
F19 E19 G19
C196 4.7U_0805_10V4Z +1.5VS_DDRDLL
2
1
2
D
C551 0.022U_0402_16V7K
B28 A28 A27
2
1
C550 C225 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2
2
1
C40 0.1U_0402_16V4Z
+2.5VS +2.5VS
1
2
+3VS_TVDACC L24 CHB1608U301_0603 1 2 1 1 +3VS_ATVBG L25 1 2 2 2 CHB1608U301_0603 1 1 +2.5VS
C243 0.1U_0402_16V4Z
B22 B21 A21
1
2
+2.5VS
+1.5VS
1
1
C18 0.1U_0402_16V4Z
VCCHV0 VCCHV1 VCCHV2
+2.5VS
1
L23 CHB1608U301_0603 1 2
C226 0.022U_0402_16V7K C549 0.022U_0402_16V7K
+2.5VS
2
C38 10U_0805_6.3V6M
A35
2
2
C185 0.1U_0402_16V4Z
VCCA_LVDS
2
C203 0.022U_0402_16V7K
+1.5VS
1
C204 0.022U_0402_16V7K
B26 B25 A25
C200 0.1U_0402_16V4Z
VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2
C228 0.022U_0402_16V7K
VCCD_HMPLL1 VCCD_HMPLL2 VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL
D19 H17
2
C249 0.1U_0402_16V4Z
AC1 AC2 B23 C35 AA1 AA2
VCCD_TVDAC VCCDQ_TVDAC
2
1
1
C21 0.1U_0402_16V4Z
1
H18 G18
1
C194 10U_0805_6.3V6M
@
VCCA_TVBG VSSA_TVBG
POWER
1
C193 0.1U_0402_16V4Z
+2.5V
C218 0.1U_0402_16V4Z
C202 0.1U_0402_16V4Z
C212 10U_0805_6.3V6M
C24 0.1U_0402_16V4Z
C23 0.1U_0402_16V4Z
C192 0.1U_0402_16V4Z
Note: Place near chip.
+3VS_ATVBG
C547 0.22U_0603_16V4Z
2
+3VS_TVDACC
C28 220U_D2_4VM
2
1
+3VS_TVDACB
C44 100U_D2_6.3VM
2
1
F17 E17 D18 C18 F18 E18
C221 0.1U_0402_16V4Z
1
VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1
C222 0.1U_0402_16V4Z
C232 2.2U_0603_6.3V4Z
C244 0.22U_0603_16V4Z
V2.5_DDR_CAP6 V2.5_DDR_CAP4 V2.5_DDR_CAP3
VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48
+3VS_TVDACB 1
10U_0805_6.3V6M
C65 0.47U_0603_16V7K
2
T29 R29 N29 M29 K29 J29 V28 U28 T28 R28 P28 N28 M28 L28 K28 J28 H28 G28 V27 U27 T27 R27 P27 N27 M27 L27 K27 J27 H27 K26 H26 K25 J25 K24 K23 K22 K21 W20 U20 T20 K20 V19 U19 K19 W18 V18 T18 K18 K17
+1.5VS
C215 0.1U_0402_16V4Z
C245 0.47U_0603_16V7K
2
1
0.1U_0402_16V4Z
2
2
1
330U_D2E_2.5VM
2
1
2
1
Note : All VCCSM pin shorted internally.
C35 10U_0805_6.3V6M
1
1
C239 0.1U_0402_16V4Z
2
2
C246 0.1U_0402_16V4Z
1
1
C236 10U_0805_6.3V6M
2
2
+3VS_TVDACA
U5E
V2.5_DDR_CAP1 V2.5_DDR_CAP2 V2.5_DDR_CAP5
C201
1
1
W=20 mils
C216
2
+VCCP
V2.5_DDR_CAP1 V2.5_DDR_CAP2 V2.5_DDR_CAP5
AM37 AH37 AP29 AD28 AD27 AC27 AP26 AN26 AM26 AL26 AK26 AJ26 AH26 AG26 AF26 AE26 AP25 AN25 AM25 AL25 AK25 AJ25 AH25 AG25 AF25 AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18 AE17 AE16 AE15 AE14 AP13 AN13 AM13 AL13 AK13 AJ13 AH13 AG13 AF13 AE13 AP12 AN12 AM12 AL12 AK12 AJ12 AH12 AG12 AF12 AE12 AD11 AC11 AB11 AB10 AB9 AP8 AM1 AE1
C248
C
1
VCCSM0 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8 VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36 VCCSM37 VCCSM38 VCCSM39 VCCSM40 VCCSM41 VCCSM42 VCCSM43 VCCSM44 VCCSM45 VCCSM46 VCCSM47 VCCSM48 VCCSM49 VCCSM50 VCCSM51 VCCSM52 VCCSM53 VCCSM54 VCCSM55 VCCSM56 VCCSM57 VCCSM58 VCCSM59 VCCSM60 VCCSM61 VCCSM62 VCCSM63 VCCSM64
C214 0.1U_0402_16V4Z
C217 4.7U_0805_10V4Z
+VCCP
POWER
C254 0.22U_0603_16V4Z
D
VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT35 VTT36 VTT37 VTT38 VTT39 VTT40 VTT41 VTT42 VTT43 VTT44 VTT45 VTT46 VTT47 VTT48 VTT49 VTT50 VTT51
+3VS
L22 CHB1608U301_0603 1 2
C227 0.022U_0402_16V7K C224 0.1U_0402_16V4Z
U5F K13 J13 K12 W11 V11 U11 T11 R11 P11 N11 M11 L11 K11 W10 V10 U10 T10 R10 P10 N10 M10 K10 J10 Y9 W9 U9 R9 P9 N9 M9 L9 J9 N8 M8 N7 M7 N6 M6 A6 N5 M5 N4 M4 N3 M3 N2 M2 B2 V1 N1 M1 G1
1
+3VS_TVDACA
Route VSSATVBG gnd from GMCH to decoupling cap ground lead and then connect to the gnd plane.
C182 0.01U_0402_16V7K
3
C17 10U_0805_6.3V6M
4
C16 10U_0805_6.3V6M
5
1
2
A
A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
Alviso(4 of 5) Sheet
Tuesday, February 15, 2005 1
Rev 0.2 10
of
46
5
4
+VCCP
C
B
A
VTT_NCTF17 VTT_NCTF16 VTT_NCTF15 VTT_NCTF14 VTT_NCTF13 VTT_NCTF12 VTT_NCTF11 VTT_NCTF10 VTT_NCTF9 VTT_NCTF8 VTT_NCTF7 VTT_NCTF6 VTT_NCTF5 VTT_NCTF4 VTT_NCTF3 VTT_NCTF2 VTT_NCTF1 VTT_NCTF0
Y12 AA12 Y13 AA13 L14 M14 N14 P14 R14 T14 U14 V14 W14 Y14 AA14 AB14 L15 M15 N15 P15 R15 T15 U15 V15 W15 Y15 AA15 AB15 L16 M16 N16 P16 R16 T16 U16 V16 W16 Y16 AA16 AB16 R17 Y17 AA17 AB17 AA18 AB18 AA19 AB19 AA20 AB20 R21 Y21 AA21 AB21 Y22 AA22 AB22 Y23 AA23 AB23 Y24 AA24 AB24 Y25 AA25 AB25 Y26 AA26 AB26
VSS_NCTF68 VSS_NCTF67 VSS_NCTF66 VSS_NCTF65 VSS_NCTF64 VSS_NCTF63 VSS_NCTF62 VSS_NCTF61 VSS_NCTF60 VSS_NCTF59 VSS_NCTF58 VSS_NCTF57 VSS_NCTF56 VSS_NCTF55 VSS_NCTF54 VSS_NCTF53 VSS_NCTF52 VSS_NCTF51 VSS_NCTF50 VSS_NCTF49 VSS_NCTF48 VSS_NCTF47 VSS_NCTF46 VSS_NCTF45 VSS_NCTF44 VSS_NCTF43 VSS_NCTF42 VSS_NCTF41 VSS_NCTF40 VSS_NCTF39 VSS_NCTF38 VSS_NCTF37 VSS_NCTF36 VSS_NCTF35 VSS_NCTF34 VSS_NCTF33 VSS_NCTF32 VSS_NCTF31 VSS_NCTF30 VSS_NCTF29 VSS_NCTF28 VSS_NCTF27 VSS_NCTF26 VSS_NCTF25 VSS_NCTF24 VSS_NCTF23 VSS_NCTF22 VSS_NCTF21 VSS_NCTF20 VSS_NCTF19 VSS_NCTF18 VSS_NCTF17 VSS_NCTF16 VSS_NCTF15 VSS_NCTF14 VSS_NCTF13 VSS_NCTF12 VSS_NCTF11 VSS_NCTF10 VSS_NCTF9 VSS_NCTF8 VSS_NCTF7 VSS_NCTF6 VSS_NCTF5 VSS_NCTF4 VSS_NCTF3 VSS_NCTF2 VSS_NCTF1 VSS_NCTF0
V25 W25 L26 M26 N26 P26 R26 T26 U26 V26 W26
VCC_NCTF10 VCC_NCTF9 VCC_NCTF8 VCC_NCTF7 VCC_NCTF6 VCC_NCTF5 VCC_NCTF4 VCC_NCTF3 VCC_NCTF2 VCC_NCTF1 VCC_NCTF0
VCCSM_NCTF31 VCCSM_NCTF30 VCCSM_NCTF29 VCCSM_NCTF28 VCCSM_NCTF27 VCCSM_NCTF26 VCCSM_NCTF25 VCCSM_NCTF24 VCCSM_NCTF23 VCCSM_NCTF22 VCCSM_NCTF21 VCCSM_NCTF20 VCCSM_NCTF19 VCCSM_NCTF18 VCCSM_NCTF17 VCCSM_NCTF16 VCCSM_NCTF15 VCCSM_NCTF14 VCCSM_NCTF13 VCCSM_NCTF12 VCCSM_NCTF11 VCCSM_NCTF10 VCCSM_NCTF9 VCCSM_NCTF8 VCCSM_NCTF7 VCCSM_NCTF6 VCCSM_NCTF5 VCCSM_NCTF4 VCCSM_NCTF3 VCCSM_NCTF2 VCCSM_NCTF1 VCCSM_NCTF0 VCC_NCTF78 VCC_NCTF77 VCC_NCTF76 VCC_NCTF75 VCC_NCTF74 VCC_NCTF73 VCC_NCTF72 VCC_NCTF71 VCC_NCTF70 VCC_NCTF69 VCC_NCTF68 VCC_NCTF67 VCC_NCTF66 VCC_NCTF65 VCC_NCTF64 VCC_NCTF63 VCC_NCTF62 VCC_NCTF61 VCC_NCTF60 VCC_NCTF59 VCC_NCTF58 VCC_NCTF57 VCC_NCTF56 VCC_NCTF55 VCC_NCTF54 VCC_NCTF53 VCC_NCTF52 VCC_NCTF51 VCC_NCTF50 VCC_NCTF49 VCC_NCTF48 VCC_NCTF47 VCC_NCTF46 VCC_NCTF45 VCC_NCTF44 VCC_NCTF43 VCC_NCTF42 VCC_NCTF41 VCC_NCTF40 VCC_NCTF39 VCC_NCTF38 VCC_NCTF37 VCC_NCTF36 VCC_NCTF35 VCC_NCTF34 VCC_NCTF33 VCC_NCTF32 VCC_NCTF31 VCC_NCTF30 VCC_NCTF29 VCC_NCTF28 VCC_NCTF27 VCC_NCTF26 VCC_NCTF25 VCC_NCTF24 VCC_NCTF23 VCC_NCTF22 VCC_NCTF21 VCC_NCTF20 VCC_NCTF19 VCC_NCTF18 VCC_NCTF17 VCC_NCTF16 VCC_NCTF15 VCC_NCTF14 VCC_NCTF13 VCC_NCTF12 VCC_NCTF11
2
1
+2.5V
U5H
L12 M12 N12 P12 R12 T12 U12 V12 W12 L13 M13 N13 P13 R13 T13 U13 V13 W13
NCTF
D
3
D
AB12 AC12 AD12 AB13 AC13 AD13 AC14 AD14 AC15 AD15 AC16 AD16 AC17 AD17 AC18 AD18 AC19 AD19 AC20 AD20 AC21 AD21 AC22 AD22 AC23 AD23 AC24 AD24 AC25 AD25 AC26 AD26 L17 M17 N17 P17 T17 U17 V17 W17 L18 M18 N18 P18 R18 Y18 L19 M19 N19 P19 R19 Y19 L20 M20 N20 P20 R20 Y20 L21 M21 N21 P21 T21 U21 V21 W21 L22 M22 N22 P22 R22 T22 U22 V22 W22 L23 M23 N23 P23 R23 T23 U23 V23 W23 L24 M24 N24 P24 R24 T24 U24 V24 W24 L25 M25 N25 P25 R25 T25 U25
U5I Y1 D2 G2 J2 L2 P2 T2 V2 AD2 AE2 AH2 AL2 AN2 A3 C3 AA3 AB3 AC3 AJ3 C4 H4 L4 P4 U4 Y4 AF4 AN4 E5 W5 AL5 AP5 B6 J6 L6 P6 T6 AA6 AC6 AE6 AJ6 G7 V7 AA7 AG7 AK7 AN7 C8 E8 L8 P8 Y8 AL8 A9 H9 K9 T9 V9 AA9 AC9 AE9 AH9 AN9 D10 L10 Y10 AA10 F11 H11 Y11
+VCCP
VSS271 VSS270 VSS269 VSS268 VSS260 VSS259 VSS258 VSS257 VSS256 VSS255 VSS254 VSS253 VSS252 VSS251 VSS250 VSS249 VSS248 VSS247 VSS246 VSS245 VSS244 VSS243 VSS242 VSS241 VSS240 VSS239 VSS238 VSS237 VSS236 VSS235 VSS234 VSS233 VSS232 VSS231 VSS230 VSS229 VSS228 VSS227 VSS226 VSS225 VSS224 VSS223 VSS222 VSS221 VSS220 VSS219 VSS218 VSS217 VSS216 VSS215 VSS214 VSS213 VSS212 VSS211 VSS210 VSS209 VSS208 VSS207 VSS206 VSS205 VSS204 VSS203 VSS202 VSS201 VSS200 VSS199 VSS198 VSS197 VSS196
VSSALVDS
VSS
VSS195 VSS194 VSS193 VSS192 VSS191 VSS190 VSS189 VSS188 VSS187 VSS186 VSS185 VSS184 VSS183 VSS182 VSS181 VSS180 VSS179 VSS178 VSS177 VSS176 VSS175 VSS174 VSS173 VSS172 VSS171 VSS170 VSS169 VSS168 VSS167 VSS166 VSS165 VSS164 VSS163 VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS150 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130
U5J AL24 AN24 A26 E26 G26 J26 B27 E27 G27 W27 AA27 AB27 AF27 AG27 AJ27 AL27 AN27 E28 W28 AA28 AB28 AC28 A29 D29 E29 F29 G29 H29 L29 P29 U29 V29 W29 AA29 AD29 AG29 AJ29 AM29 C30 Y30 AA30 AB30 AC30 AE30 AP30 D31 E31 F31 G31 H31 J31 K31 L31 M31 N31 P31 R31 T31 U31 V31 W31 AD31 AG31 AL31 A32 C32 Y32 AA32 AB32
B36 AA11 AF11 AG11 AJ11 AL11 AN11 B12 D12 J12 A14 B14 F14 J14 K14 AG14 AJ14 AL14 AN14 C15 K15 A16 D16 H16 K16 AL16 C17 G17 AF17 AJ17 AN17 A18 B18 U18 AL18 C19 H19 J19 T19 W19 AG19 AN19 A20 D20 E20 F20 G20 V20 AK20 C21 F21 AF21 AN21 A22 D22 E22 J22 AH22 AL22 H23 AF23 B24 D24 F24 J24 AG24 AJ24
VSS267 VSS266 VSS265 VSS264 VSS263 VSS262 VSS261 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100 VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85 VSS84 VSS83 VSS82 VSS81 VSS80 VSS79 VSS78 VSS77 VSS76 VSS75 VSS74 VSS73 VSS72 VSS71 VSS70 VSS69 VSS68
VSS
ALVISO_BGA1257
AC32 AD32 AJ32 AN32 D33 E33 F33 G33 H33 J33 K33 L33 M33 N33 P33 R33 T33 U33 V33 W33 AD33 AF33 AL33 C34 AA34 AB34 AC34 AD34 AH34 AN34 B35 D35 E35 F35 G35 H35 J35 K35 L35 M35 N35 P35 R35 T35 U35 V35 W35 Y35 AE35 C36 AA36 AB36 AC36 AD36 AE36 AF36 AJ36 AL36 AN36 E37 H37 K37 M37 P37 T37 V37 Y37 AG37
C
B
ALVISO_BGA1257
A
ALVISO_BGA1257 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
VSS67 VSS66 VSS65 VSS64 VSS63 VSS62 VSS61 VSS60 VSS59 VSS58 VSS57 VSS56 VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0
4
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
Alviso(5 of 5) Sheet
Tuesday, February 15, 2005 1
Rev 0.1 11
of
46
A
8 DDR_A_D[0..63] 8 DDR_A_DM[0..7]
B
DDR_A_D[0..63]
DDR_D[0..63]
DDR_A_DM[0..7]
DDR_DM[0..7]
DDR_A_DQS[0..7]
8 DDR_A_DQS[0..7]
C
DDR_DQS[0..7]
DDR_A_DM0 DDR_A_DQS0 1
DDR_A_D6 DDR_A_D2 DDR_A_D3 DDR_A_D7
4 3 2 1
5 6 7 8 10_1206_8P4R_5% 1 2 R118 1 10_0402_5% 2 R111 RP23 10_0402_5% 4 5 3 6 2 7 1 8 10_1206_8P4R_5%
DDR_A_DM1 DDR_A_DQS1 DDR_A_D14 DDR_A_D15 DDR_A_D10 DDR_A_D11
4 3 2 1
5 6 7 8 10_1206_8P4R_5% 1 2 R121 1 10_0402_5% 2 R123 RP25 10_0402_5% 4 5 3 6 2 7 1 8 10_1206_8P4R_5%
DDR_DQS[0..7] 13
DDR_D6 DDR_D2 DDR_D3 DDR_D7
DDR_D8 DDR_D13 DDR_D9 DDR_D12 DDR_DM1 DDR_DQS1 DDR_D14 DDR_D15 DDR_D10 DDR_D11
DDR_A_DM2 DDR_A_DQS2 DDR_A_D19 DDR_A_D18 DDR_A_D22 DDR_A_D23
2
4 3 2 1
5 6 7 8 10_1206_8P4R_5% 1 2 R127 1 10_0402_5% 2 R126 RP29 10_0402_5% 4 5 3 6 2 7 1 8 10_1206_8P4R_5%
DDR_A_DQS3 DDR_A_DM3 DDR_A_D28 DDR_A_D30 DDR_A_D31 DDR_A_D27
4 3 2 1
5 6 7 8 10_1206_8P4R_5% 1 2 R129 1 10_0402_5% 2 R130 RP33 10_0402_5% 4 5 3 6 2 7 1 8 10_1206_8P4R_5%
U2 7 7
DDR_CLK1 DDR_CLK1#
7 7
DDR_CLK0 DDR_CLK0#
7
DDR_CKE0
8 8
DDR_A_BS#0 DDR_A_BS#1
7
DDR_SCS#0
8 8 8
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
DDR_DQS0 DDR_DM0 DDR_D0 DDR_D1 DDR_D4 DDR_D5 DDR_D6 DDR_D2 DDR_D3 DDR_D7
DDR_CLK1 DDR_CLK1# DDR_CLK0 DDR_CLK0# DDR_CKE0 DDR_A_BS#0 DDR_A_BS#1
DDR_DQS1 DDR_DM1 DDR_D8 DDR_D13 DDR_D9 DDR_D12 DDR_D14 DDR_D15 DDR_D10 DDR_D11
DDR_SCS#0 DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
DDR_D17 DDR_D16 DDR_D21 DDR_D20
7,13
SDREF
SDREF
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12
1
DDR_DM2 DDR_DQS2
C25 0.1U_0402_16V4Z
DDR_D19 DDR_D18 DDR_D22 DDR_D23
2
Close pin49
DDR_D24 DDR_D25 DDR_D29 DDR_D26 DDR_DQS3 DDR_DM3
DDR_A_DQS4 DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D35 DDR_A_D34 3
4 3 2 1
5 6 7 8 10_1206_8P4R_5% 1 2 R144 1 10_0402_5% 2 R145 RP35 10_0402_5% 4 5 3 6 2 7 1 8 10_1206_8P4R_5%
DDR_A_DQS5 DDR_A_DM5 DDR_A_D46 DDR_A_D47 DDR_A_D43 DDR_A_D42
4 3 2 1
5 6 7 8 10_1206_8P4R_5% 1 2 R155 1 10_0402_5% 2 R150 RP37 10_0402_5% 4 5 3 6 2 7 1 8 10_1206_8P4R_5%
DDR_A_DM6 DDR_A_DQS6 DDR_A_D54 DDR_A_D55 DDR_A_D50 DDR_A_D51
4 3 2 1
5 6 7 8 10_1206_8P4R_5% 1 2 R161 1 10_0402_5% 2 R162 RP39 10_0402_5% 4 5 3 6 2 7 1 8 10_1206_8P4R_5%
4
51 47 54 56 57 59 60 62 63 65
UDQS UDM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
49
VREF
29 30 31 32 35 36 37 38 39 40 28 41 42
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AP/A10 A11 A12
VDD0 VDD1 VDD2 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 NC0 NC1 NC2 NC3 NC4 NC5 NC6
14 17 19 25 43 50 53
CK CK# CKE
45 46 44
DDR_CLK0 DDR_CLK0# DDR_CKE0
BA0 BA1
26 27
DDR_A_BS#0 DDR_A_BS#1
CS# RAS# CAS# WE#
24 23 22 21
DDR_SCS#0 DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSS0 VSS1 VSS2
6 12 52 58 64 34 48 66
1 C4 1 C137 1 C27 1 C26
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
DDR_A_MA13
16 20 2 4 5 7 8 10 11 13
LDQS LDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DDR_DQS3 DDR_DM3 DDR_D24 DDR_D25 DDR_D29 DDR_D26 DDR_D28 DDR_D30 DDR_D31 DDR_D27
51 47 54 56 57 59 60 62 63 65
UDQS UDM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
49
VREF
29 30 31 32 35 36 37 38 39 40 28 41 42
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AP/A10 A11 A12
SDREF 1 C56 0.1U_0402_16V4Z
Close pin49
2
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12
VDD0 VDD1 VDD2 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4
1 18 33 3 9 15 55 61
NC0 NC1 NC2 NC3 NC4 NC5 NC6
14 17 19 25 43 50 53
CK CK# CKE
45 46 44
DDR_CLK0 DDR_CLK0# DDR_CKE0
BA0 BA1
26 27
DDR_A_BS#0 DDR_A_BS#1
CS# RAS# CAS# WE#
24 23 22 21
VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSS0 VSS1 VSS2
6 12 52 58 64 34 48 66
1 C46 1 C47 1 C58 1 C57
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
1
DDR_A_MA13
DDR_SCS#0 DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
2
HY5DU121622A(L)T-J_TSOPII66
+2.5V RP26
U7 DDR_A_BS#0 5 DDR_A_MA12 6 DDR_A_BS#1 7 DDR_A_MA10 8 56_1206_8P4R_5%
4 3 2 1
DDR_D36 DDR_D37 DDR_D33 DDR_D32
+2.5V U4
RP27 DDR_A_MA1 5 DDR_A_MA2 6 DDR_A_MA5 7 DDR_A_MA3 8 56_1206_8P4R_5%
4 3 2 1
DDR_DQS4 DDR_DM4
RP32 DDR_A_MA4 5 DDR_A_MA6 6 DDR_A_MA0 7 DDR_A_MA7 8 56_1206_8P4R_5%
4 3 2 1
DDR_D38 DDR_D39 DDR_D35 DDR_D34
RP31 4 3 2 1
DDR_A_MA8 5 DDR_A_MA9 6 DDR_A_MA11 7 DDR_A_MA13 8 56_1206_8P4R_5%
1
2 56_0402_5%
DDR_CKE0
1
2 56_0402_5%
DDR_SCS#0
1 R139 1 R119 1 R135
2 56_0402_5% 2 56_0402_5% 2 56_0402_5%
DDR_A_WE# DDR_A_RAS# DDR_A_CAS#
DDR_D45 DDR_D44 DDR_D41 DDR_D40 DDR_DQS5 DDR_DM5 DDR_D46 DDR_D47 DDR_D43 DDR_D42
R124 R122
DDR_DQS4 DDR_DM4 DDR_D36 DDR_D37 DDR_D33 DDR_D32 DDR_D38 DDR_D39 DDR_D35 DDR_D34
16 20 2 4 5 7 8 10 11 13
LDQS LDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DDR_DQS5 DDR_DM5 DDR_D45 DDR_D44 DDR_D41 DDR_D40 DDR_D46 DDR_D47 DDR_D43 DDR_D42
51 47 54 56 57 59 60 62 63 65
UDQS UDM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
SDREF 1 C41 0.1U_0402_16V4Z
RP38 DDR_A_D49 DDR_A_D52 DDR_A_D53 DDR_A_D48
LDQS LDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
1 18 33 3 9 15 55 61
+1.25VS
DDR_D28 DDR_D30 DDR_D31 DDR_D27
RP36 DDR_A_D45 DDR_A_D44 DDR_A_D41 DDR_A_D40
16 20 2 4 5 7 8 10 11 13
DDR_DQS2 DDR_DM2 DDR_D17 DDR_D16 DDR_D21 DDR_D20 DDR_D19 DDR_D18 DDR_D22 DDR_D23
HY5DU121622A(L)T-J_TSOPII66
RP34 DDR_A_D36 DDR_A_D37 DDR_A_D33 DDR_A_D32
H
U3 +2.5V
RP30 DDR_A_D24 DDR_A_D25 DDR_A_D29 DDR_A_D26
G
+2.5V
DDR_DM0 DDR_DQS0
RP28 DDR_A_D17 DDR_A_D16 DDR_A_D21 DDR_A_D20
F
Samsung K4H511638B-TC/LB3-SA116380000 Option-R217,R220(Del R221),R277(Del R283) Infineon HYB25D512160AT-6-SA121600000(GM) Default-R217,R221,R283 Hynix HY5DU121622AT-J-SA216220000(A die)->SA000023200(B die)(PM) Option-R217,R220(Del R221),R283
DDR_A_MA[0..13]
8 DDR_A_MA[0..13]
DDR_D0 DDR_D1 DDR_D4 DDR_D5
RP24 DDR_A_D8 DDR_A_D13 DDR_A_D9 DDR_A_D12
E
DDR_D[0..63] 13 DDR_DM[0..7] 13
RP22 DDR_A_D0 DDR_A_D1 DDR_A_D4 DDR_A_D5
D
DDR_D49 DDR_D52 DDR_D53 DDR_D48
Close pin49
DDR_DM6 DDR_DQS6
2
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12
49
VREF
29 30 31 32 35 36 37 38 39 40 28 41 42
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AP/A10 A11 A12
VDD0 VDD1 VDD2 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4
1 18 33 3 9 15 55 61
NC0 NC1 NC2 NC3 NC4 NC5 NC6
14 17 19 25 43 50 53
CK CK# CKE
45 46 44
BA0 BA1
26 27
CS# RAS# CAS# WE#
24 23 22 21
VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSS0 VSS1 VSS2
6 12 52 58 64 34 48 66
1 C30 1 C29 1 C43 1 C42
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
DDR_A_MA13
DDR_CLK1 DDR_CLK1# DDR_CKE0
16 20 2 4 5 7 8 10 11 13
LDQS LDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DDR_DQS7 DDR_DM7 DDR_D61 DDR_D60 DDR_D56 DDR_D57 DDR_D62 DDR_D59 DDR_D63 DDR_D58
51 47 54 56 57 59 60 62 63 65
UDQS UDM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
49
VREF
SDREF
DDR_A_BS#0 DDR_A_BS#1 DDR_SCS#0 DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
DDR_DQS6 DDR_DM6 DDR_D49 DDR_D52 DDR_D53 DDR_D48 DDR_D54 DDR_D55 DDR_D50 DDR_D51
1 C74 0.1U_0402_16V4Z
Close pin49
2
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12
29 30 31 32 35 36 37 38 39 40 28 41 42
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AP/A10 A11 A12
VDD0 VDD1 VDD2 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4
1 18 33 3 9 15 55 61
NC0 NC1 NC2 NC3 NC4 NC5 NC6
14 17 19 25 43 50 53
CK CK# CKE
45 46 44
BA0 BA1
26 27
CS# RAS# CAS# WE#
24 23 22 21
VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSS0 VSS1 VSS2
6 12 52 58 64 34 48 66
1 C62 1 C61 1 C76 1 C75
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
DDR_A_MA13
3
DDR_CLK1 DDR_CLK1# DDR_CKE0 DDR_A_BS#0 DDR_A_BS#1 DDR_SCS#0 DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
HY5DU121622A(L)T-J_TSOPII66
HY5DU121622A(L)T-J_TSOPII66
DDR_D54 DDR_D55 DDR_D50 DDR_D51 4
RP40 DDR_A_D61 DDR_A_D60 DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_DQS7 DDR_A_D62 DDR_A_D59 DDR_A_D63 DDR_A_D58
A
4 3 2 1
5 6 7 8 10_1206_8P4R_5% 1 2 R171 1 10_0402_5% 2 R166 RP41 10_0402_5% 4 5 3 6 2 7 1 8 10_1206_8P4R_5% B
DDR_D61 DDR_D60 DDR_D56 DDR_D57 DDR_DM7 DDR_DQS7
Compal Electronics, Inc. Title
DDR_D62 DDR_D59 DDR_D63 DDR_D58
DDR-SODIMM SLOT0 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C
D
E
F
Size
Document Number
Rev 0.1
LA-2592 Date:
Tuesday, February 15, 2005 G
Sheet
12 H
of
46
A
B
C
D
+2.5V
+2.5V
+1.25VS
E
JP18
DDR_DM0 DDR_DQS0 R5 R6 1
DDR_D2 DDR_D6 DDR_D7 DDR_D3
1 1
RP2
4 3 2 1
8 7 6 5 56_1206_8P4R_5% 2 56_0402_5% 2 56_0402_5% 5 6 7 8 56_1206_8P4R_5%
DDR_D1 DDR_D0 DDR_DQS0 DDR_D5 DDR_D4 DDR_D15 DDR_D[0..63]
DDR_D[0..63] 12
DDR_DM[0..7] 4 3 2 1 DDR_DM1 DDR_DQS1 R7 R8 DDR_D15 DDR_D14 DDR_D11 DDR_D10
1 1
RP3
1 2 3 4
5 6 7 8 56_1206_8P4R_5% 2 56_0402_5% 2 56_0402_5% 8 7 6 5 56_1206_8P4R_5%
DDR_D11 DDR_D10
DDR_DM[0..7] 12
RP4 DDR_D13 DDR_D8 DDR_D12 DDR_D9
DDR_D14 DDR_DQS1
DDR_DQS[0..7]
DDR_DQS[0..7] 12
8 DDR_B_MA[0..13]
7 7
DDR_B_MA[0..13]
DDR_CLK3 DDR_CLK3#
DDR_D16 DDR_D17 DDR_DQS2 DDR_D20 DDR_D21 DDR_D30
RP5 DDR_D16 DDR_D17 DDR_D20 DDR_D21
1 2 3 4 DDR_DM2 DDR_DQS2 R16 R15
2
DDR_D18 DDR_D19 DDR_D23 DDR_D22
1 1
RP6
4 3 2 1
DDR_D28 DDR_DQS3
8 7 6 5 56_1206_8P4R_5% 2 56_0402_5% 2 56_0402_5% 5 6 7 8 56_1206_8P4R_5%
DDR_D27 DDR_D31
RP8 DDR_D25 DDR_D24 DDR_D26 DDR_D29
4 3 2 1 DDR_DM3 DDR_DQS3 R17 R18
DDR_D30 DDR_D28 DDR_D27 DDR_D31
1 1
RP7
1 2 3 4
5 6 7 8 56_1206_8P4R_5% 2 56_0402_5% 2 56_0402_5% 8 7 6 5 56_1206_8P4R_5%
+1.25VS
DDR_D39 DDR_D38 DDR_D34 DDR_D35
8 7 6 5 56_1206_8P4R_5% 1 2 56_0402_5% 1 2 RP15 56_0402_5% 4 5 3 6 2 7 1 8 56_1206_8P4R_5%
RP11
DDR_D47 DDR_D46 DDR_D42 DDR_D43
DDR_DQS4 DDR_D32
DDR_B_MA2 4 DDR_B_MA1 3 DDR_B_MA10 2 DDR_B_MA0 1 56_1206_8P4R_5%
R21 R20 R22
8 7 6 5
DDR_B_BS#1 1 DDR_B_BS#0 2 DDR_SCS#2 3 DDR_SCS#3 4 56_1206_8P4R_5%
1 1 1
DDR_B_WE# 2 56_0402_5% DDR_B_RAS# 2 56_0402_5% DDR_B_CAS# 2 56_0402_5%
DDR_D33 DDR_D47 DDR_D46 DDR_DQS5 DDR_D42 DDR_D43
DDR_D52 DDR_D49 DDR_DQS6 DDR_D48 DDR_D53 DDR_D59
RP18 DDR_D52 DDR_D49 DDR_D48 DDR_D53
1 2 3 4
DDR_D55 DDR_D54 DDR_D51 DDR_D50
8 7 6 5 56_1206_8P4R_5% 1 2 56_0402_5% 1 2 RP19 56_0402_5% 4 5 3 6 2 7 1 8 56_1206_8P4R_5%
DDR_D62 DDR_DQS7 DDR_D58 DDR_D63 18 18
CK_SDATA CK_SCLK
CK_SDATA CK_SCLK +3VS
DDR_D60 DDR_D61 DDR_D57 DDR_D56
VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS
DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 CK2# VDD CKE1 DU/A13 A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 WE# S0# DU VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDD_SPD VDD_ID AMP_1565917-1
RP21 4
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS
201
DDR_DM6 DDR_DQS6 R30 R31
DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# DDR_SCS#2 DDR_D37 DDR_D36
RP13
4 3 2 1 DDR_DM5 DDR_DQS5 R28 R29
DDR_B_BS#0 DDR_B_WE# DDR_SCS#2
RP12 5 6 7 8
RP17 5 6 7 8 56_1206_8P4R_5% 1 2 56_0402_5% 1 2 RP16 56_0402_5% 1 8 2 7 3 6 4 5 56_1206_8P4R_5%
8 8 7
DDR_B_MA6 1 DDR_B_MA5 2 DDR_B_MA3 3 DDR_B_MA4 4 56_1206_8P4R_5%
8 7 6 5
3
DDR_D44 DDR_D45 DDR_D40 DDR_D41
DDR_B_MA11 4 DDR_B_MA9 3 DDR_B_MA7 2 DDR_B_MA8 1 56_1206_8P4R_5%
5 6 7 8
DDR_CKE3 DDR_B_MA13 DDR_B_MA12 DDR_B_MA9 DDR_B_MA7 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
RP10
1 2 3 4 DDR_DM4 DDR_DQS4 R23 R26
DDR_CKE3
DDR_CKE2 1 DDR_CKE3 2 DDR_B_MA13 3 DDR_B_MA12 4 56_1206_8P4R_5%
8 7 6 5
RP14 DDR_D37 DDR_D36 DDR_D32 DDR_D33
7 RP9
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
SDREF
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
DDR_D2 DDR_D6 DDR_DM0 DDR_D7
SDREF
1
2
7,12
C135 0.1U_0402_16V4Z
DDR_D3 DDR_D13 1
DDR_D8 DDR_DM1 DDR_D12 DDR_D9
DDR_D18 DDR_D19
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
DDR_DM2 DDR_D23 DDR_D22 DDR_D25 DDR_D24 DDR_DM3 DDR_D26 DDR_D29
2
DDR_CKE2
DDR_CKE2 7
DDR_B_MA11 DDR_B_MA8 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS#1 DDR_B_RAS# DDR_B_CAS# DDR_SCS#3
DDR_B_BS#1 8 DDR_B_RAS# 8 DDR_B_CAS# 8 DDR_SCS#3 7
DDR_D39 DDR_D38 DDR_DM4 DDR_D34 DDR_D35 DDR_D44 3
DDR_D45 DDR_DM5 DDR_D40 DDR_D41 DDR_CLK4# 7 DDR_CLK4 7 DDR_D55 DDR_D54 DDR_DM6 DDR_D51 DDR_D50 DDR_D60 DDR_D61 DDR_DM7 DDR_D57 DDR_D56 +3VS
4
4 3 2 1 DDR_DM7 DDR_DQS7 R36 R39
DDR_D59 DDR_D62 DDR_D58 DDR_D63
A
5 6 7 8 56_1206_8P4R_5% 1 2 56_0402_5% 1 2 RP20 56_0402_5% 1 8 2 7 3 6 4 5 56_1206_8P4R_5%
DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU/RESET# VSS VSS VDD VDD CKE0 DU/BA2 A11 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# S1# DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU VSS
1 2 3 4
202
DDR_D1 DDR_D0 DDR_D5 DDR_D4
VSS
RP1
Compal Electronics, Inc. Title
DDR-SODIMM SLOT1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
C
D
Size
Document Number
Rev 0.2
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 E
13
of
46
A
B
C
D
E
Layout note : Distribute as close as possible to DDR-SODIMM.
+2.5V
1
1
2
1 C139 0.1U_0402_16V4Z
2
1 C138 0.1U_0402_16V4Z
2
1 C142 0.1U_0402_16V4Z
2
1 C181 0.1U_0402_16V4Z
2
1 C140 0.1U_0402_16V4Z
2
1 C144 0.1U_0402_16V4Z
2
+2.5V
1
2
2
1 C187 0.1U_0402_16V4Z
2
1 C197 0.1U_0402_16V4Z
2
1 C219 0.1U_0402_16V4Z
2
1
C238 0.1U_0402_16V4Z
+2.5V
1 C233 0.1U_0402_16V4Z
1 C189 0.1U_0402_16V4Z
2
1 C241 0.1U_0402_16V4Z
2
1 C208 0.1U_0402_16V4Z
2
1 C240 0.1U_0402_16V4Z
2
1 C251 0.1U_0402_16V4Z
2
1 C231 0.1U_0402_16V4Z
1
+
+ C3 @ 150U_D_6.3VM 2
2
C77 150U_D_6.3VM
Layout note : Place one cap close to every 2 pull up resistors termination to +1.25V
+1.25VS 2
2
1
2
1 C32 0.1U_0402_16V4Z
2
1 C9 0.1U_0402_16V4Z
2
1 C14 0.1U_0402_16V4Z
2
1 C49 0.1U_0402_16V4Z
2
1 C184 0.1U_0402_16V4Z
2
1 C207 0.1U_0402_16V4Z
2
1 C191 0.1U_0402_16V4Z
2
1 C206 0.1U_0402_16V4Z
2
1 C143 0.1U_0402_16V4Z
2
C161 0.1U_0402_16V4Z
+1.25VS
1
2
1 C183 0.1U_0402_16V4Z
2
1 C190 0.1U_0402_16V4Z
2
1 C6 0.1U_0402_16V4Z
2
1 C162 0.1U_0402_16V4Z
2
1 C71 0.1U_0402_16V4Z
2
1 C67 0.1U_0402_16V4Z
2
1 C72 0.1U_0402_16V4Z
2
1 C66 0.1U_0402_16V4Z
2
1 C55 0.1U_0402_16V4Z
2
C52 0.1U_0402_16V4Z
+1.25VS
1
2
1 C50 0.1U_0402_16V4Z
2
1 C51 0.1U_0402_16V4Z
2
1 C39 0.1U_0402_16V4Z
2
1 C37 0.1U_0402_16V4Z
2
1 C213 0.1U_0402_16V4Z
2
1 C33 0.1U_0402_16V4Z
2
1 C34 0.1U_0402_16V4Z
2
1 C36 0.1U_0402_16V4Z
2
1 C31 0.1U_0402_16V4Z
2
C210 0.1U_0402_16V4Z
+1.25VS 3
3
1
2
1 C48 0.1U_0402_16V4Z
2
1 C64 0.1U_0402_16V4Z
2
1 C179 0.1U_0402_16V4Z
2
1 C10 0.1U_0402_16V4Z
2
1 C180 0.1U_0402_16V4Z
2
1 C5 0.1U_0402_16V4Z
2
1 C53 0.1U_0402_16V4Z
2
1 C7 0.1U_0402_16V4Z
2
1 C63 0.1U_0402_16V4Z
2
C45 0.1U_0402_16V4Z
4
4
Compal Electronics, Inc. Title
DDR SODIMM Decoupling THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Size Document Number Custom LA-2592 Date:
Rev 0.2 Sheet
Tuesday, February 15, 2005 E
14
of
46
5
4
3
2
C
1
1
B
E 2222
2
3
SYMBOL(SOT23-NEW)
D
D
+3VS
1
1
C69 0.1U_0402_16V4Z
2
R34 @ 10K_0402_5% U8
2
H_THERMDA
4 H_THERMDA
1
VDD
SCLK
8
SMB_EC_CK2
2
D+
SDATA
7
SMB_EC_DA2
3
D-
ALERT#
6
GND
5
1
C
H_THERMDC
4 H_THERMDC
C68 2200P_0402_50V7K
2
4
THERM#
SMB_EC_CK2 29,33 C
SMB_EC_DA2 29,33
ADM1032AR_SOP8
+5VS +12VALW
C229
C223 2 1 1 2 5 6
U6A
OUT
FAN1_ON
1
+3VS
3
S
B
SI3456DV-T1_TSOP6 1
LM358A_SO8
R27 10K_0402_5% 2
4
FAN1 Control and Tachometer
G
+IN
2 -IN FAN1_VFB
4
3
EN_FAN1
G
33 B
2
10U_0805_10V4Z D Q20
P
0.1U_0402_16V4Z
8
1
FAN1SPD 33
R24 100K_0402_5% 2 1
1 JP19 1
1
C59 C60 10U_0805_10V4Z 2 2 0.1U_0402_16V4Z D2 1N4148_SOT23
1 2 3
C54 1000P_0402_50V7K
2
ACES_85205-0300
2
FAN1 3
R25 150K_0402_5% 1 2
FAN1_VOUT 1
A
A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
Thermal sensor and Fan Sheet
Tuesday, February 15, 2005 1
15
of
46
Rev 0.2
3
2
1
SP020025900
34
+LCDVDD
D
PEG_TXP4 PEG_TXN4 PEG_TXP5 PEG_TXN5 PEG_TXP6 PEG_TXN6 PEG_TXP7 PEG_TXN7 PEG_TXP8 PEG_TXN8 PEG_TXP9 PEG_TXN9 PEG_TXP10 PEG_TXN10 PEG_TXP11 PEG_TXN11 PEG_TXP12 PEG_TXN12
C176 1 C158 1 C174 1 C156 1 C172 1 C154 1 C170 1 C152 1 C168 1 C150 1 C166 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
C12
PEG_RXP1 PEG_RXN1
0.1U_0402_16V4Z
1
2
2
C13
LVDSA1+ LVDSA1-
0.1U_0402_16V4Z
PEG_RXP2 PEG_RXN2
LVDSA2LVDSA2+
PEG_RXP3 PEG_RXN3
LVDSACLVDSAC+
PEG_RXP4 PEG_RXN4
DAC_BRIG INVTPWM DISPLAYOFF#
PEG_RXP5 PEG_RXN5 +3VS
I2CC_SCL I2CC_SDA
PEG_RXP6 PEG_RXN6 +LCDVDD PEG_RXP7 PEG_RXN7
AT LEAST 60 MIL
PEG_RXP8 PEG_RXN8
INVPWR_B+
PEG_RXP9 PEG_RXN9
34
1
JP3 LVDS_A0+ LVDS_A0-
9 9
LVDS_A1+ LVDS_A1-
9 9
LVDS_A2LVDS_A2+
9 9
LVDS_ACLVDS_AC+
33
DAC_BRIG
LVDS_A1+ LVDS_A1LVDS_A2LVDS_A2+ LVDS_ACLVDS_AC+ DAC_BRIG INVTPWM DISPLAYOFF# LCDP_CLK LCDP_DAT
+3VS +LCDVDD
AT LEAST 60 MIL Inverter B+ INVPWR_B+ R12 2 1 0_0805_5%
CONNVGA@ ACES_20184-3000
VGA@ PCIE_MTX_C_GRX_P13 0.1U_0402_16V4Z 2 PCIE_MTX_C_GRX_N13 VGA@ PCIE_MTX_C_GRX_P14 0.1U_0402_16V4Z 2 PCIE_MTX_C_GRX_N14 VGA@ PCIE_MTX_C_GRX_P15 0.1U_0402_16V4Z 2 PCIE_MTX_C_GRX_N15
1 C148
1 C147 VGA@ 1 C164 0.1U_0402_16V4Z 2 1 C163 VGA@ 1 C146 0.1U_0402_16V4Z 2 1 C145 VGA@ 0.1U_0402_16V4Z 2
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
LVDS_A0+ LVDS_A0-
9 9
D
CONNVGA@ ACES_20184-3000 34
PEG_TXP3 PEG_TXN3
C160 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
LVDSA0+ LVDSA0-
33
PEG_TXP2 PEG_TXN2
C177 1 2 VGA@ 0.1U_0402_16V4Z C159 1 2 VGA@ 0.1U_0402_16V4Z C175 1 2 VGA@ 0.1U_0402_16V4Z C157 1 2 VGA@ 0.1U_0402_16V4Z C173 1 2 VGA@ 0.1U_0402_16V4Z C155 1 2 VGA@ 0.1U_0402_16V4Z C171 1 2 VGA@ 0.1U_0402_16V4Z C153 1 2 VGA@ 0.1U_0402_16V4Z C169 1 2 VGA@ 0.1U_0402_16V4Z C151 1 2 VGA@ 0.1U_0402_16V4Z C167 1 2 VGA@ 0.1U_0402_16V4Z C149 1 2 VGA@ 0.1U_0402_16V4Z C165 1 2 VGA@ 0.1U_0402_16V4Z
PEG_RXP0 PEG_RXN0
33
PEG_TXP1 PEG_TXN1
JP16
VGA@ PCIE_MTX_C_GRX_P0 2 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N0 VGA@ PCIE_MTX_C_GRX_P1 2 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N1 VGA@ PCIE_MTX_C_GRX_P2 2 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P3 2 PCIE_MTX_C_GRX_N3 VGA@ PCIE_MTX_C_GRX_P4 2 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N4 VGA@ PCIE_MTX_C_GRX_P5 2 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N5 VGA@ PCIE_MTX_C_GRX_P6 2 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N6 VGA@ PCIE_MTX_C_GRX_P7 2 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N7 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P8 2 PCIE_MTX_C_GRX_N8 VGA@ PCIE_MTX_C_GRX_P9 2 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N9 VGA@ PCIE_MTX_C_GRX_P10 2 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N10 VGA@ PCIE_MTX_C_GRX_P11 2 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N11 VGA@ PCIE_MTX_C_GRX_P12 2 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N12
C1781
33
JP2 PEG_TXP0 PEG_TXN0
33
4
34
5
PEG_TXP13 PEG_TXN13
Aviso LCD/PANEL BD. CONN.
PEG_TXP14 PEG_TXN14
+LCDVDD PEG_TXP15 PEG_TXN15
+12VALW
+LCDVDD
R102 470_0402_5%
R88 100K_0402_5%
D
S
C
+3VS
Q1 SI2302DS_SOT23 3
R87 100K_0402_5%
1
C
C1
2
G
SP010009100
1
1
0.1U_0402_16V4Z D Q3 2N7002_SOT23
B
PEG_RXP13 PEG_RXN13 PEG_RXP14 PEG_RXN14 PEG_RXP15 PEG_RXN15
17 COMP/B_VGA 17 Y/G_VGA 17 C/R_VGA
3
2 1 2VREF
41
SUSP# SUSP
33,34,35,40,41 35,40
9
R14
[email protected]_0402_5%
NV44_ENBKL 33
R10 NONVGA@ 2.2K_0402_5%
Q5 PLTRST_VGA# 19,21 9
SMBCLK_VGA SMBDAT_VGA
LCD_CLK
SMBCLK_VGA 17 SMBDAT_VGA 17
VGA_RED VGA_GRN VGA_BLU
BK_EN
33
BKOFF#
3
+2.5VS LCD EEPROM
VGA_RED 17 VGA_GRN 17 VGA_BLU 17
1
D13
R1 1
INVT_PWM
LCD_DAT
3
1
LCDP_DAT
R2 9
1
BIA
NONVGA@ BSS138_SOT23
VGA@
VGA@
2
NONVGA@ 0_0402_5% R3 VGA_BIA 1
1
4
INVTPWM
@ NC7SZ14M5X_SOT23-5
2
2
R52 A
VGA@ 100K_0402_5%
VGA@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
Y
1
33
U1
A
VGA@ 0_0402_5% LVDSBIA LVDSBIA
Title
5
2
2
2
VGA@
2
1
C130 0.047U_0402_16V4Z
VGA@
0.1U_0402_16V4Z C131
0.1U_0402_16V4Z C132
0.1U_0402_16V4Z C134
0.1U_0402_16V4Z C133
VGA@
1
1
C129 0.047U_0402_16V4Z
VGA@
1
C128 0.047U_0402_16V4Z
A
1
2
0_0402_5% 2 +3VS
D
1
2
RB751V_SOD323
LCDP_CLK 33
S
9 +3VS
2
B
D1 NONVGA@ RB751V_SOD323 2 R9 1 NONVGA@ 100K_0402_5% 1 2
Q6
2
DISPLAYOFF#
2
NONVGA@ BSS138_SOT23
ACES_88366-8071 +5VALW
3
3
SUSP# SUSP VGA_BIA NV44_ENBKL ENVDD PLTRST_VGA# I2CC_SCL I2CC_SDA
1
G
COMP/B_VGA Y/G_VGA C/R_VGA
4.7K_0402_5% +3VS
D
VSYNC_VGA HSYNC_VGA
VSYNC_VGA HSYNC_VGA
R120
G
17 17
+3VS +3VS
5
PEG_RXP12 PEG_RXN12
ENVDD
P
PEG_RXP11 PEG_RXN11
2
G
PEG_RXN[0:15] 9
2
3
PEG_RXN[0:15]
PEG_RXP10 PEG_RXN10
PEG_RXP[0:15] 9
1
NONVGA@ 0_0402_5%
1
PEG_RXP[0:15]
LVDSACLVDSAC+
PEG_TXN[0..15] 9
R96
EN_LCDVDD
1
PEG_TXN[0..15]
LVDSA2LVDSA2+
PEG_TXP[0..15] 9
R4 150K_0402_5%
S Q2 DTC124EK_SC59
2
PEG_TXP[0..15]
9 +5VALW
2
LVDSA1+ LVDSA1-
C2 0.1U_0402_16V4Z
Q18 2N7002_SOT23
2
LVDSA0+ LVDSA0-
S
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
S
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
D
2 G
2
18 CLK_PCIE_VGA 18 CLK_PCIE_VGA#
2 G
1
B+
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
VGA/B connector Sheet
Tuesday, February 15, 2005 1
16
Rev 0.3 of
46
5
4
3
TV-Out Connector
2
1
VGA I/O PORT Connector For EMI +5VS +2.5VS
D
9 16
Y/G Y/G_VGA
9 16
R90
1 VGA@ 2 0_0402_5%
R103 1NONVGA@2 0_0402_5%
C/R C/R_VGA
9
R98
NONVGA@ 1 2 0_0402_5%
COMP/B
16 COMP/B_VGA
R93
1 VGA@ 2 0_0402_5%
R97
1NONVGA@2 0_0402_5%
R89
1 VGA@ 2 0_0402_5%
LUMA C554
CRMA
34 ON/OFFBTN# 33 MSEN# 33 ON/OFFBTN_LED# 33 LID_SW#
COMPS
+3VS
For EMI 2
C553
C555 0.1U_0402_16V4Z 2 1
+3VS
2
D
0.1U_0402_16V4Z 1 1 0.1U_0402_16V4Z +5VS +3VS +2.5VS ON/OFFBTN# MSEN# ON/OFFBTN_LED# LID_SW# CRT_SMBDAT CRT_SMBCLK CRT_HSYNC CRT_VSYNC CRT_R CRT_G CRT_B
JP15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+5VS +3VS NUMLOCK# CAPLOCK# SCROLLLOCK# WL/BT_ON BT_LED USBP6+ USBP6-
NUMLOCK# 33 CAPLOCK# 33 SCROLLLOCK# 33 WL/BT_ON 28,33 BT_LED 28 USBP6+ USBP6-
21 21
LUMA COMPS CRMA
ACES_87216-3002
C
C
1
CRT CONNECTOR 16
VGA_RED
R95
1 VGA@ 2 0_0402_5%
1
+2.5VS
R116
R117
VGA_GRN
16
VGA_BLU
R91
1 VGA@ 2 0_0402_5%
R94
1 VGA@ 2 0_0402_5%
R101 1NONVGA@2 0_0402_5%
9
CRT_GRN
R100 1NONVGA@2 0_0402_5%
CRT_G
9
CRT_BLU
R104 1NONVGA@2 0_0402_5%
CRT_B
16
HSYNC_VGA
R109 1
R113 NONVGA@ CLK_DDC2 1 2 0_0402_5%
CLK_DDC2 9
DAT_DDC2 R112 1NONVGA@2 0_0402_5%
DAT_DDC2 9
CRT_SMBDAT
R107 1 VGA@ 2 0_0402_5% SMBDAT_VGA
SMBDAT_VGA 16
CRT_SMBCLK
R106 1 VGA@ 2 0_0402_5% SMBCLK_VGA
SMBCLK_VGA 16
CRT_R
CRT_RED
9
NONVGA@ 2.2K_0402_5% 2
16
2
NONVGA@ 2.2K_0402_5%
VGA@2 0_0402_5%
B
B
R114 1NONVGA@2 0_0402_5%
CRT_HSYNC 2
HSYNC
1
9
R108
9
VSYNC
R110 1 VGA@ 2 0_0402_5% R115 1NONVGA@2 0_0402_5%
R105
VGA@ 2.2K_0402_5% CRT_VSYNC
VGA@ 2.2K_0402_5% 1
VSYNC_VGA
2
16
+3VS
A
A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
TV_OUT and DVI connector Rev 0.2 Sheet
Tuesday, February 15, 2005 1
17
of
46
5
4
3
+3VS
3
1 2 L15 CHB1608U301_0603
1
2
1
C483 10U_0805_10V4Z
1
1
1
1
C473 0.047U_0402_16V4Z 2
C435 0.047U_0402_16V4Z 2
2
CK_SDATA 13
Q36 2N7002_SOT23
Place near each pin W>40 mil
2 G
+CK_VDD_MAIN2
ICH_SMBCLK
Q38 3 2N7002_SOT23
CK_SCLK
1 L14 CHB1608U301_0603
CK_SCLK 13
S
D
1
2 2
2N7002
2
2
1
2
2
0 0 1 for Dothan-B 533Mhz 1 0 1 for Dothan-B 400Mhz FSC
FSB
FSA
CLKSEL0
CLKSEL1
CLKSEL2
0
0
0
C
*
2
100
X1 C431 33P_0402_50V8J 2 1
33.3
0
0
1
133
100
33.3
0
1
0
200
100
33.3
0
1
1
166
100
33.3
21 28 34 1 7
1
CK_XTAL_IN 14.318MHZ_20P_1BX14318CC1A
1
42 48 2CK_VDD_REF
R338 1_0603_5% 2CK_VDD_4811 R368 2.2_0603_5% 50
CK_XTAL_OUT
CLK_48M_CB CLK_48M_ICH CLKSEL0
25 CLK_48M_CB 21 CLK_48M_ICH
U28
Place crystal within 500 mils of CKGEN
C428 33P_0402_50V8J 2 1
CPU SRC PCI MHz MHz MHz 266
1
C433 0.047U_0402_16V4Z
S
1
1
3
1
1 R399 1 R415
714@ 2 12_0402_5% 2 12_0402_5%
49 CLKSEL2
PS: When CB714 unpop, R415 12 Ohm change to 33 Ohm CLKSEL1
1
0
0
333
100
33.3
1
0
1
100
100
33.3
CLK_33M_CBS
25 CLK_33M_CBS
CLK_33M_1394
27 CLK_33M_1394
CLK_33M_MPCI
28 CLK_33M_MPCI
1
1
0
1
1
0
100
400
RESERVED
33.3
CLK_33M_LAN
24 CLK_33M_LAN
CLK_33M_ICH
19 CLK_33M_ICH
CLK_33M_LPCEC
33 CLK_33M_LPCEC
Table : ICS 954226
+3VS
2 R375 2 R378 2 R377 2 R354 2 R379 2 R376 1 R385
PCICLK5 1 33_0402_5% PCICLK4 1 33_0402_5% PCICLK3 1 33_0402_5% PCICLK2 1 33_0402_5% PCICLKF1 1 33_0402_5% 1 33_0402_5% PCICLKF0 2 10K_0402_5% CK_SCLK
+VCCP
CK_SDATA
2
B
1 R323
R329
2
2
1
1
4.7K_0402_5%
C429 C477 0.047U_0402_16V4Z 0.047U_0402_16V4Z 2 2 R367 2.2_0603_5% CK_VDD_A 1 2
VDDPCIEX_0 VDDPCIEX_1 VDDPCIEX_2
1
37 38
VDDPCI_0 VDDPCI_1
55
H_STP_PCI#
CPU_STOP#
54
H_STP_CPU#
CPUCLKT1
41
CK_CPU1
CPUCLKC1
40
CK_CPU1#
CPUCLKT0
44
CK_CPU0
CPUCLKC0
43
CK_CPU0#
VDD48
FSLB/TEST_MODE
CPUCLKT2_ITP/PCIEXT6
36
CK_CPU2
CPUCLKC2_ITP/PCIEXC6
35
CK_CPU2#
5
PCICLK5
4
PCICLK4
PEREQ1#/PCIEXT5
33
3
PCICLK3
PEREQ2#/PCIEXC5
32
46
H_STP_PCI# 21 H_STP_CPU# 21,42
PCICLK2/REQ_SEL PCIEXT4
31
SRC5
PCIEXC4
30
SRC5#
ITP_EN/PCICLK_F0
SATACLKT
26
SRC4
SCLK
SATACLKC
27
SRC4#
SELPCIEX_LCDCLK#/PCICLK_F1
47
SDATA
39
IREF
13
+3VS R340 @ 10K_0402_5%
1
1
R389 10K_0402_5% CLKSEL2
2
+VCCP
1 R356 1 R357
CLK_MCH_BCLK 2 33_0402_5% CLK_MCH_BCLK# 2 33_0402_5%
1 R341 1 R342
CLK_CPU_BCLK 2 33_0402_5% CLK_CPU_BCLK# 2 33_0402_5%
PCIEXT3
24
PCIEXC3
25
PCIEXT2
22
1 R343 1 R344
CLK_ITP 2 @ 33_0402_5% CLK_ITP# 2 @ 33_0402_5%
1 R352 1 R353
CLK_MCH_3GPLL 2 33_0402_5% CLK_MCH_3GPLL# 2 33_0402_5%
1 R380 1 R381
CLK_PCIE_VGA 2 33_0402_5% CLK_PCIE_VGA# 2 33_0402_5%
2
PCIEXC2
23
PCIEXT1
19
SRC1
PCIEXC1
20
SRC1# SRC0 SRC0#
GND_0
29
GND_1
LCDCLK_SS/PCIEX0T
17
2
GND_2
LCDCLK_SS/PCIEX0C
18
45
GND_3
51
GND_4
DOTT_96MHz DOTC_96MHz
14 15
6
GND_5
1 R410 1 R411
CLK_PCIE_ICH 2 33_0402_5% CLK_PCIE_ICH# 2 33_0402_5%
SSC_DREFCLK 1 2 R382 NONVGA@ 33_0402_5% SSC_DREFCLK# 1 2 R383 NONVGA@ 33_0402_5%
DOTCLK R408 1 NONVGA@ 2 33_0402_5% DREFCLK DOTCLK# DREFCLK# 1 2 R409 NONVGA@ 33_0402_5%
2 2
49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1%
R418 NONVGA@ 49.9_0402_1% 1 2
DREFCLK#
1 2 R419 NONVGA@ 49.9_0402_1%
CLK_MCH_BCLK 7 CLK_MCH_BCLK# 7
CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4
CLK_ITP
4
CLK_ITP#
4
CLK_MCH_3GPLL 9 CLK_MCH_3GPLL# 9 CLK_PCIE_VGA 16 CLK_PCIE_VGA# 16
CLK_PCIE_ICH 21 CLK_PCIE_ICH# 21 SSC_DREFCLK 7 SSC_DREFCLK# 7 DREFCLK 7 DREFCLK# 7
+3VS
21,42 2
VGATE
REF0
52
CLKREF
1 R355
CLK_14M_ICH 2 33_0402_5%
1
10
MCH_CLKSEL1 7
D CLK_14M_ICH 21
2 G
Q42 2N7002_SOT23 S
3
ICS954226AGT_TSSOP56
1K_0402_5%
2
VTT_PWRGD#/PD
R400
1 1
R394 0_0402_5%
2
D
49.9_0402_1%
A
Table : ICS 954226
2
CPU_BSEL1
2
49.9_0402_1%
DREFCLK
R398 10K_0402_5%
R395 @ 10K_0402_5% 1
5
2
49.9_0402_1%
R390 NONVGA@ 49.9_0402_1% 1 2 R391 NONVGA@ 49.9_0402_1% 1 2
1
10K_0402_5%
A
2
49.9_0402_1%
B
R416 @ 10K_0402_5%
1
1
49.9_0402_1%
SSC_DREFCLK#
R401
2
1
MCH_CLKSEL0 7
1K_0402_5%
CLKSEL1
1
49.9_0402_1%
C
X2
16
8
1
49.9_0402_1%
X1
FS_A/USB_48MHz REF1/FSLC/TEST_SEL
9
CLK_CPU_BCLK
1
VDDCPU VDDREF
12 53
56
1
SSC_DREFCLK
PCI/SRC_STOP#
2
R339 0_0402_5%
VDDA GNDA
2
CPU_BSEL0
1
2
5
CLKIREF 2 475_0402_1%
Place near ICS954226
1
10K_0402_5% R331
R451 CLKSEL0
10U_0805_10V4Z
CK_VDD_REF
2
G 2
C444 4.7U_0805_10V4Z
1
CK_VDD_48 1
C475 0.047U_0402_16V4Z
CK_VDD_A
C460 4.7U_0805_10V4Z
D
C434 0.047U_0402_16V4Z
1
1
C469
2 R332 CLK_MCH_BCLK# 2 R333
2 R321 CLK_CPU_BCLK# 2 R322 CLK_ITP 2 R319 CLK_ITP# 2 R320 CLK_PCIE_VGA 1 R392 CLK_PCIE_VGA# 1 R393 CLK_PCIE_ICH 1 R420 CLK_PCIE_ICH# 1 R421 CLK_MCH_3GPLL 1 R345 CLK_MCH_3GPLL# 1 R346
2
+3VS
21 ICH_SMBCLK
CLK_MCH_BCLK C478 0.047U_0402_16V4Z
1
D
1
C432 0.047U_0402_16V4Z 2
2 G
1
C474 0.1U_0402_16V4Z CK_SDATA
S
D
ICH_SMBDATA
21 ICH_SMBDATA
R349 10K_0402_5% 2 1
R330 10K_0402_5% 2 1
+3VS
2
+CK_VDD_MAIN
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
Clock Generator Sheet
Tuesday, February 15, 2005 1
18
Rev 0.1 of
46
5
4
3
2
1
RP45 U9B
8 7 6 5
PCI_PERR# PCI_DEVSEL# PCI_PLOCK# PCI _IRDY#
8.2K_0804_8P4R_5% RP44 +3VS
1 2 3 4
8 7 6 5
PCI_PIRQC# PCI_PIRQH# PCI_PIRQD# PCI_PIRQB#
8.2K_0804_8P4R_5%
8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5%
1 1 1 1
2 2 2 2
R241 R274 R265 R279
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQA# 24,25,27,28 PCI_FRAME#
C
+3VS
+3VS
+3VALW
8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5%
8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5%
1 1 1 1
1 1 1
1 R254
2 2 2 2
R269 R268 R245 R262
2 R255 2 R244 2 R261
25 25
PCI_REQ0# PCI_REQ1# PCI_REQ3# PCI_REQ4#
PCI_PIRQA# PCI_PIRQB#
PCI_FRAME# PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
J3
ICH_PME# 2 @ 10K_0402_1%
PCI_C_BE0# PCI_C_BE1# PCI_C_BE2# PCI_C_BE3#
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY#
A3 E1 R2 C3 E3 C5 G5 J1 J2
PCI _IRDY# PCI_PAR PCI_PCIRST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY#
PLTRST# PCICLK PME#
R5 G6 P6
PLTRST# CLK_33M_ICH ICH_PME#
+3VALW C117 0.1U_0402_16V4Z 2 1
PLTRST# PCI_REQ5#
1 2
PCI_REQ6#
A
U13A
PCI_C_BE0# PCI_C_BE1# PCI_C_BE2# PCI_C_BE3#
24,25,27,28 24,25,27,28 24,25,27,28 24,25,27,28
R71 3
O B
D
1
33_0402_5% 2
PLTRST_VGA# 16,21
SN74LVC08APW_TSSOP14
PLTRST_SWDJ# 23
+3VALW
4
PCI_IRDY# 24,25,27,28 PCI_PAR 24,25,27,28
5
A
U13B R63 6
O B
PCI_DEVSEL# 24,25,27,28 PCI_PERR# 24,25,27,28
PCIRSTB2#
1
33_0402_5% 2
PLTRST_MCH# 7,21,25,27
SN74LVC08APW_TSSOP14
PCI_SERR# 24,25,27,28 PCI_STOP# 24,25,27,28 PCI_TRDY# 24,25,27,28 +3VALW
FRAME# PIRQ[A]# PIRQ[B]# PIRQ[C]# PIRQ[D]#
24 24 25 25 27 27 28 28
14
J6 H6 G4 G2
PCI_REQ0# PCI_GNT0# PCI_REQ1# PCI_GNT1# PCI_REQ2# PCI_GNT2# PCI_REQ3# PCI_GNT3#
P
C/BE[0]# C/BE[1]# C/BE[2]# C/BE[3]#
Interrupt N2 L2 M1 L3 AC5 AD5 AF4 AG4 AC9 AD9 AF8 AG8 U3
PCI_REQ2# PCI_REQ5# PCI_REQ6#
PCI_REQ0# PCI_GNT0# PCI_REQ1# PCI_GNT1# PCI_REQ2# PCI_GNT2# PCI_REQ3# PCI_GNT3# PCI_REQ4#
G
1 2 3 4
L5 C1 B5 B6 M5 F1 B8 C8 F7 E7 E8 F6 B7 D8
7
RP43 +3VS
REQ[0]# GNT[0]# REQ[1]# GNT[1]# REQ[2]# GNT[2]# REQ[3]# GNT[3]# REQ[4]#/GPI[40] GNT[4]#/GPO[48] REQ[5]#/GPI[1] GNT[5]#/GPO[17] REQ[6]#/GPI[0] GNT[6]#/GPO[16]
PCI
14
D
AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31]
P
8.2K_0804_8P4R_5%
E2 E5 C2 F5 F3 E9 F2 D6 E6 D3 A2 D2 D5 H3 B4 J5 K2 K5 D4 L6 G3 H4 H2 H5 B3 M6 B2 K6 K3 A5 L1 K4
G
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
7
24,25,27,28 PCI_AD[0..31]
I/F D9 C7 C6 M3
PIRQ[E]#/GPI[2] PIRQ[F]#/GPI[3] PIRQ[G]#GPI[4] PIRQ[H]#/GPI[5]
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
14
PCI_SERR# PCI_FRAME# PCI_TRDY# PCI_STOP#
CLK_33M_ICH 18 ICH_PME# 24,28,33
PCI_PCIRST#
9 10
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
27 24 28 28
A
U13C
P
8 7 6 5
8PCIRSTB3#1
O B
R61 33_0402_5% 2
PCIRST# 24,25,27,28,33
G
1 2 3 4
7
+3VS
C
SN74LVC08APW_TSSOP14
RESERVED SATA[1]RXN/RSVD[1] SATA[1]RXP/RSVD[2] SATA[1]TXN/RSVD[3] SATA[1]TXP/RSVD[4] SATA[3]RXN/RSVD[5] SATA[3]RXP/RSVD[6] SATA[3]TXN/RSVD[7] SATA[3]TXP/RSVD[8] TP[3]/RSVD[9] ICH6_BGA609 CLK_33M_ICH
to 42 k
SA8280108G0 S IC 030 FW82801FBM B2 BGA 609P ICH6-M -> SA8280108E0(R3)/SA8280108D0(R1) S IC 030 FW82801FBM QS ICH6-M BGA 609P 2
PME# signal has an integrated pull-up of 18 k
1
R264 @ 10_0402_5%
1
2
C348 @ 8.2P_0402_50V
B
B
A
A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Compal Electronics, Inc.
Size Document Number Custom LA-2592 Date:
ICH6(1/4) Sheet
Tuesday, February 15, 2005 1
Rev 0.1 19
of
46
5
4
3
2
1
BATT1.1
+RTCVCC
2
CHGRTC
ML1220T13RE
RB751V_SOD323
2
NC
IN
1
3
NC
OUT
4
+RTCVCC
+RTCVCC
1
R67 20K_0402_5%
ICH_RTCX2 ICH_RTCRST#
2
INTRUDER#
1
JOPEN1 1 2
R69
SHORT PADS 2
RTCRST#
AA3 AA5
INTRUDER# INTVRMEN
BITCLK
2
29,30
IAC_SYNC
29,30
IAC_RST# IAC_SDATAI0 IAC_SDATAI1
1
R239 29 10_0402_5% 30 @ 2
LAN_CLK
B11
LAN_RSTSYNC
E12 E11 C13
LANRXD[0] LANRXD[1] LANRXD[2]
1
1
1 B
R190 @ 8.2K_0402_5%
1
IDE_ HIORDY
IDE_HIRQ
23 23 23 23 23
IDE_HIORDY IDE_HIRQ IDE_HDACK# IDE_HDIOW# IDE_HDIOR#
H_FERR#
CPUPWRGD/GPO[49]
AG25
H_PW RGOOD
IGNNE# INIT3_3V# INIT# INTR
AG26 AE22 AF27 AG24
H_IGNNE#
RCIN#
AD23
KBRST#
NMI SMI#
AF25 AG27
H_NMI H_SMI#
F11 F10 B10
ACZ_SDIN[0] ACZ_SDIN[1] ACZ_SDIN[2]
2 R234 24.9_0402_1%
ACZ_SDO
SATA[0]RXN SATA[0]RXP SATA[0]TXN SATA[0]TXP
AD7 AC7 AF6 AG6
SATA[2]RXN SATA[2]RXP SATA[2]TXN SATA[2]TXP
AC2 AC1
SATA_CLKN SATA_CLKP
AG11 AF11
SATARBIAS# SATARBIAS
IDE_ HIORDY IDE_HIRQ IDE_HDACK# IDE_HDIOW# IDE_HDIOR#
AF16 AB16 AB15 AC14 AE16
IORDY IDEIRQ DDACK# DIOW# DIOR#
H_INIT# H_INTR
STPCLK#
AE26
H_STPCLK#
THRMTRIP#
AE23
THRMTRIP_ICH# 1
DA[0] DA[1] DA[2]
AC16 AB17 AC17
IDE_HDA0 IDE_HDA1 IDE_HDA2
DCS1# DCS3#
AD16 AE17
IDE_HDCS1# IDE_HDCS3#
DD[0] DD[1] DD[2] DD[3] DD[4] DD[5] DD[6] DD[7] DD[8] DD[9] DD[10] DD[11] DD[12] DD[13] DD[14] DD[15]
AD14 AF15 AF14 AD12 AE14 AC11 AD11 AB11 AE13 AF13 AB12 AB13 AC13 AE15 AG15 AD13
IDE_HDD0 IDE_HDD1 IDE_HDD2 IDE_HDD3 IDE_HDD4 IDE_HDD5 IDE_HDD6 IDE_HDD7 IDE_HDD8 IDE_HDD9 IDE_HDD10 IDE_HDD11 IDE_HDD12 IDE_HDD13 IDE_HDD14 IDE_HDD15
DDREQ
AB14
IDE_HDREQ
SATALED#
AE3 AD3 AG2 AF2
GATEA20 H_A20M# 1 @ 0_0402_5% H_CPUSLP#
AF24
LANTXD[0] LANTXD[1] LANTXD[2]
2
2
R187 @ 4.7K_0402_5%
CPUSLP# R45
FERR#
IAC_SDATAI0 IAC_SDATAI1
SATABIAS# close as ICH6 0.5"
GATEA20 H_A20M#
LPC_LFRAME# 33
H_DPRSLP# H_DPSLP#
ACZ_RST#
+3VS
AF22 AF23
SATA
+3VS
A20GATE A20M#
H_FERR#
R203 56_0402_5% 2 1
H_DPRSLP#
R202 56_0402_5% 2 1
LPC_LDRQ0# 33
AE24 AD27
A10
AC19
LFRAME#/FWH[4]
LPC_LFRAME#
CPUSLP#
IAC_RST#
C9
LPC_LDRQ0#
P3
DPRSLP#/TP[4] DPSLP#/TP[2]
ACZ_BIT_CLK ACZ_SYNC
IAC_SDATO
29,30 IAC_SDATO
N6 P4
H_FERR# close as ICH6 0.5" +VCCP
AE27
C10 B9
C326 @ 10P_0402_50V8J
LDRQ[0]# LDRQ[1]#/GPI[41]
AC-97/AZALIA
29,30 BITCLK
LAD[0]/FWH[0] LAD[1]/FWH[1] LAD[2]/FWH[2] LAD[3]/FWH[3]
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
EE_CS EE_SHCLK EE_DOUT EE_DIN
F12
C12 C11 E13
C
RTCX1 RTCX2
P2 N3 N5 N4
LAN
C114 1U_0603_10V4Z 1 2
D
LPC_LAD[0..3] 33
AA2
D12 B12 D11 F13
1M_0402_5% INTRUDER#
U9A Y1 Y2
RTC
C113 32.768KHZ_12.5P_1TJS125DJ2A073 18P_0402_50V8J 2 1
2
33 4
H_CPUSLP# 4,7 H_DPRSLP# 4 H_DPSLP# 4 H_FERR# 4
MAINPWRON 36,38,39 R193 @ 330_0402_5% 1 2 2 B 1 2
H_PWRGOOD 4 H_IGNNE# 4 H_INIT# H_INTR
+VCCP
4 4
KBRST# 33 H_NMI H_SMI#
+VCCP
4 4
1
1
0.1U_0402_16V4Z
ICH_RTCX1
Y2
D7
C
Q21 @ 2SC2411K_SC59 E
3
C115 18P_0402_50V8J 2 1
PIDE
1
2
LPC
D
100_0603_1% C116
BATT1
1
W=20mils
R65 10M_0402_5% 2 1
2
2
CPU
+
R70 1
C264 @ 1U_0603_10V4Z 1 2 R194 75_0402_5%
H_THERMTRIP# C
4,7 H_THERMTRIP# H_STPCLK# 4 2 R201 H_THERMTRIP# 56_0402_5% IDE_HDA0 23 IDE_HDA1 23 IDE_HDA2 23 IDE_HDCS1# 23 IDE_HDCS3# 23 IDE_HDD[0..15] 23
B
IDE_HDREQ 23
ICH6_BGA609
A
A
Compal Electronics, Inc. Title
ICH6(2/4) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size
Document Number
Rev 0.2
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 1
20
of
46
5
4
3
2
+3VALW
33_0402_5%
1
ICH_SMBCLK ICH_SMBDATA LINKALERT# ICH_SMLINK0 ICH_SMLINK1 MCH_SYNC# SPKR
2
R209 10K_0402_5% CLKRUN#
29
Requires a PU Resistor to Vcc3_3(CRB uses 8.2K to Vcc3_3) CLK RUN no work to pull down
34
SPKR SUS_STAT#
4 ITP_DBRESET# 7 PM_BMBUSY#
CLK_14M_ICH CLK_48M_ICH
EC_SMI#
33 33
LID_SWOUT# EC_SCI#
2 2
R186 @ 10_0402_5%
18
H_STP_PCI#
C327 @ 4.7P_0402_50V8C
2
2
1
1
W3
SUS_STAT#/LPCPD#
ITP_DBRESET#
U2
SYS_RESET#
PM_BMBUSY#
AD19
BM_BUSY#/GPI[6]
GPI7 EC_SMI#
AE19 R1
GPI[7] GPI[8]
STP_PCI#/GPO[18]
AB21
GPO[19]
H_STP_CPU#
AD22
STP_CPU#/GPO[20]
2 @ 10K_0402_5% 2 @ 0_0402_5%
AD20 AD21
GPO[21] GPO[23]
V3
GPIO[24]
18,42 H_STP_CPU# C269 R210 1 1 R204
+3VS 16,19 PLTRST_VGA#
@ 4.7P_0402_50V8C
23
IDE_HRESET#
23
IDE_DRESET#
P5 R3 T3 AF19 AF20 AC18
GPIO27 CLKRUN#
RE R283 10K_0402_5% 2
2
2
DDR RAM 32Mb*16*4 Vendor ID
1
1
1
RC
GPI7 GPIO27
1
1
1
GPIO34
RF
R218 @ 10K_0402_5%
R221 10K_0402_5%
R277 @ 10K_0402_5% 2
RD 2
RB 2
B
GPI[12] GPI[13]
AC21
GPIO34
R220 @ 10K_0402_5%
SMBALERT#/GPI[11]
M2 R6
SB_INT_FLASH_SEL#
34 EC_FLASH# 24,27,28,33 CLKRUN#
RA
W6
H_STP_PCI#
34 SB_INT_FLASH_SEL#
+3VS
R217 10K_0402_5%
SMBCLK SMBDATA LINKALERT# SMLINK[0] SMLINK[1] MCH_SYNC# SPKR
EC_SCI#
1
1
@ 10_0402_5%
Y4 W5 Y5 W4 U6 AG21 F8
GPI7/GPIO27/GPIO34 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 1 0 1 1 0 1 1 1 1
Vendor Reserved Reserved Reserved Reserved Reserved Infineon Samsung Hynix
ICH_PCIE_WAKE# 25,33
18,42
SIRQ
VGATE
+3VS power plan
T35 PAD 33 33 33
SLP_S3# SLP_S4# SLP_S5#
33
ICH_PWRGD
+3VALW
R271 10K_0402_5% 1 2
+3VALW
1
R66 240_0402_5% 2
ITP_DBRESET#
+3VALW
1
R235 10K_0402_5% 2
ACIN_R
+3VALW
R64 10K_0402_5% 1 2
+3VALW
1
R267 680_0402_5% 2
ICH_PCIE_WAKE#
+3VS
1
R207 8.2K_0402_5% 2
EC_THRM#
+3VS
1
R205 10K_0402_5% MCH_SYNC# 2
+3VS
1
R211 10K_0402_5% 2
LINKALERT#
7,19,25,27 PLTRST_MCH# RSMRST#
PM_DPRSLPVR
EC_THRM#
AC20
THRM#
VGATE
AF21
VRMPWRGD
CLK_14M_ICH
E10
CLK14
CLK_48M_ICH
A27
CLK48
ICH_SUSCLK
V6
SUSCLK
SLP_S3# SLP_S4# SLP_S5#
T4 T5 T6
SLP_S3# SLP_S4# SLP_S5#
AA1 AE20
PWROK DPRSLPVR/TP[1]
ICH_BATLOW#
V2
BATLOW#/TP[0]
PWRBTN_OUT#
U1
PWRBTN#
PLTRST_MCH#
V5
LAN_RST#
RSMRST#
Y3
RSMRST#
PERn[1] PERp[1] PETn[1] PETp[1]
H25 H24 G27 G26
PERn[2] PERp[2] PETn[2] PETp[2]
K25 K24 J27 J26
PERn[3] PERp[3] PETn[3] PETp[3]
M25 M24 L27 L26
PERn[4] PERp[4] PETn[4] PETp[4]
P24 P23 N27 N26
DMI[0]RXN DMI[0]RXP DMI[0]TXN DMI[0]TXP
T25 T24 R27 R26
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
DMI[1]RXN DMI[1]RXP DMI[1]TXN DMI[1]TXP
V25 V24 U27 U26
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
DMI[2]RXN DMI[2]RXP DMI[2]TXN DMI[2]TXP
Y25 Y24 W27 W26
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
DMI[3]RXN DMI[3]RXP DMI[3]TXN DMI[3]TXP
AB24 AB23 AA27 AA26
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
DMI_CLKN DMI_CLKP
AD25 AC25
PAD PAD PAD PAD
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
7 7 7 7
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
7 7 7 7
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
7 7 7 7
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
7 7 7 7
CLK_PCIE_ICH# CLK_PCIE_ICH
DMI_ZCOMP
F24
DMI_IRCOMP
F23
OC[4]#/GPI[9] OC[5]#/GPI[10] OC[6]#/GPI[14] OC[7]#/GPI[15]
C23 D23 C25 C24
OVCUR#4 OVCUR#5 OVCUR#6 OVCUR#7
OC[0]# OC[1]# OC[2]# OC[3]#
C27 B27 B26 C26
OVCUR#0 OVCUR#1 OVCUR#2 OVCUR#3
USBP[0]N USBP[0]P USBP[1]N USBP[1]P USBP[2]N USBP[2]P USBP[3]N USBP[3]P USBP[4]N USBP[4]P USBP[5]N USBP[5]P USBP[6]N USBP[6]P USBP[7]N USBP[7]P
C21 D21 A20 B20 D19 C19 A18 B18 E17 D17 B16 A16 C15 D15 A14 B14
USBP0USBP0+ USBP1USBP1+
USBRBIAS# USBRBIAS
A22 B22
USBRBIAS1
ICH6_BGA609
T31 T33 T32 T34
C
CLK_PCIE_ICH# 18 CLK_PCIE_ICH 18 +1.5VS
R199 24.9_0402_1% DMI_IRCOMP 1 2 closed to 500 mils
USBP3USBP3+ USBP4USBP4+ USBP6USBP6+ USBP7USBP7+
OVCUR#0 32 OVCUR#3 32 USBP0USBP0+ USBP1USBP1+
32 32 32 32
USBP3USBP3+ USBP4USBP4+
32 32 32 32
USBP6USBP6+ USBP7USBP7+
17 17 32 32
+3VALW
RP42 OVCUR#5 OVCUR#7 OVCUR#6 OVCUR#2
4 3 2 1
5 6 7 8
B
10K_0804_8P4R_5%
OVCUR#1
1 R185 2 0_0402_5%
OVCUR#0
OVCUR#4
1 R200 2 0_0402_5%
OVCUR#3
2
R51 22.6_0402_1%
USBPN/USBPP impedance 45 Ohm
1
ICH_BATLOW#
SERIRQ
2 1 R284 10K_0402_5%
33
AB20
PM_DPRSLPVR
33 PWRBTN_OUT#
WAKE#
SIRQ
ICH_PWRGD
42 PM_DPRSLPVR
U5
GPIO[25] GPIO[27] GPIO[28] CLKRUN#/GPIO[32] GPIO[33] GPIO[34]
CLOCK
R238 C
SATA[0]GP/GPI[26] SATA[1]GP/GPI[29] SATA[2]GP/GPI[30] SATA[3]GP/GPI[31]
SUS_STAT#
ACIN_R
ICH6 VER1.5 GPI12 +3VS plan
AF17 AE18 AF18 AG18
POWER MGT
18 CLK_48M_ICH
33
RI#
PCI-EXPRESS
2
+3VS
T2
DIRECT MEDIA INTERFACE
R213 @1
D
U9C I CH_RI#
GPIO
ICH_SMBDATA ICH_SMBCLK ICH_SMLINK0 ICH_SMLINK1
18 ICH_SMBDATA 18 ICH_SMBCLK
USB
D
R272 10K_0402_5% 2 1
R290 10K_0402_5% 2 1
+3VALW
R219 10K_0402_5% 2 1
R292 10K_0402_5% 2
R289 2.2K_0402_5% 2 1
1
R291 2.2K_0402_5% 2 1
+3VS
2 1 R278 10K_0402_5%
+3VALW
18 CLK_14M_ICH
1
R208
2
100K_0402_5%
A
8.2 k
A
EC_THRM# 33
Signal has integrated pull-down in ICH
May need pulldown for DPRSLPVR in case the ICH6m does not set this value in time for boot.
Compal Electronics, Inc. SIRQ
Title
ICH6(3/4)
pull-up to Vcc3_3(CRB uses 10 k)
5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
3
2
Size
Document Number
Rev 0.2
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 1
21
of
46
5
4
3
2
1
+1.5VS
ICH_V5REF_SUS 2
C299 1U_0603_10V4Z
1
C297 0.1U_0402_16V4Z
1
VCC1_5[46] VCC1_5[47] VCC1_5[48] VCC1_5[49] VCC1_5[50] VCC1_5[51] VCC1_5[52] VCC1_5[53] VCC1_5[54] VCC1_5[55]
C333 +3VALW
+1.5VALW
1
+1.5VS
Vin
Vout
3
2
Near PIN AG9
1
1
C314 0.1U_0402_16V4Z
C347
2 1
GND
U18 APL5301-15DC_3P
2
2
AA7 AA8 AA9 AB8 AC8 AD8 AE8 AE9 AF9 AG9
VCC1_5[56] VCC1_5[57] VCC1_5[58] VCC1_5[59] VCC1_5[60] VCC1_5[61] VCC1_5[62] VCC1_5[63] VCC1_5[64] VCC1_5[65]
1
C298 0.1U_0402_16V4Z
ICH6_VCCPLL AC27 E26
VCCDMIPLL VCC3_3[1]
+3VS
AE1 AG10
+1.5VS
2
C359 0.1U_0402_16V4Z
C278 0.1U_0402_16V4Z
B
0.1U_0402_16V4Z
Near PIN AG5
0.1U_0402_16V4Z
2
1
Near PIN E26, E27
2
+3VS
A13 F14 G13 G14
+3VS 1 +3VALW
1_0402_5% A
1
G19
VCC1_5[78] VCC1_5[77] VCC1_5[76] VCC1_5[75] VCC1_5[74] VCC1_5[73] VCC1_5[72] VCC1_5[71] VCC1_5[70] VCC1_5[69] VCC1_5[68]
G20 F20 E24 E23 E22 E21 E20 D27 D26 D25 D24
1
VCC1_5[67]
G8
+1.5VALW 1
1
2
Near PIN A25 Near PIN A2-A6, D1-H1
2
1
Near PIN AA19
+1.5VALW
+2.5VS
AA18 A8
ICH_V5REF_RUN
V5REF_SUS
F21
ICH_V5REF_SUS
VCCUSBPLL VCCLAN3_3/VCCSUS3_3[1] VCCSUS3_3[20] VCCLAN3_3/VCCSUS3_3[2] VCCLAN3_3/VCCSUS3_3[3] VCCRTC VCCLAN3_3/VCCSUS3_3[4] VCCLAN1_5/VCCSUS1_5[2] VCCSUS3_3[1] VCCLAN1_5/VCCSUS1_5[1] VCCSUS3_3[2] VCCSUS3_3[3] V_CPU_IO[3] VCCSUS3_3[4] V_CPU_IO[2] VCCSUS3_3[5] V_CPU_IO[1] VCCSUS3_3[6] VCCSUS3_3[19] VCCSUS3_3[7] VCCSUS3_3[18] VCCSUS3_3[8] VCCSUS3_3[17] VCCSUS3_3[9] VCCSUS3_3[16] VCCSUS3_3[10] VCCSUS3_3[15] VCCSUS3_3[11] VCCSUS3_3[14] VCCSUS3_3[12] VCCSUS3_3[13]
A25 A24
+1.5VS +3VALW
1
2
AB3
+RTCVCC
G11 G10
+1.5VS
AG23 AD26 AB22
+VCCP 1
2
Near PIN AB18
Near PIN AG23 +3VALW C320 @ 0.1U_0402_16V4Z 1 2
+3VS
C331 1 2 0.1U_0402_16V4Z
VSS[86] VSS[85] VSS[84] VSS[83] VSS[82] VSS[81] VSS[80] VSS[79] VSS[78] VSS[77] VSS[76] VSS[75] VSS[74] VSS[73] VSS[72] VSS[71] VSS[70] VSS[69] VSS[68] VSS[67] VSS[66] VSS[65] VSS[64] VSS[63] VSS[62] VSS[61] VSS[60] VSS[59] VSS[58] VSS[57] VSS[56] VSS[55] VSS[54] VSS[53] VSS[52] VSS[51] VSS[50] VSS[49] VSS[48] VSS[47] VSS[46] VSS[45] VSS[44] VSS[43] VSS[42] VSS[41] VSS[40] VSS[39] VSS[38] VSS[37] VSS[36] VSS[35] VSS[34] VSS[33] VSS[32] VSS[31] VSS[30] VSS[29] VSS[28] VSS[27] VSS[26] VSS[25] VSS[24] VSS[23] VSS[22] VSS[21] VSS[20] VSS[19] VSS[18] VSS[17] VSS[16] VSS[15] VSS[14] VSS[13] VSS[12] VSS[11] VSS[10] VSS[9] VSS[8] VSS[7] VSS[6] VSS[5] VSS[4] VSS[3] VSS[2] VSS[1]
F4 F22 F19 F17 E25 E19 E18 E15 E14 D7 D22 D20 D18 D14 D13 D10 D1 C4 C22 C20 C18 C14 B25 B24 B23 B21 B19 B15 B13 AG7 AG3 AG22 AG20 AG17 AG14 AG12 AG1 AF7 AF3 AF26 AF12 AF10 AF1 AE7 AE6 AE25 AE21 AE2 AE12 AE11 AE10 AD6 AD24 AD2 AD18 AD15 AD10 AD1 AC6 AC3 AC26 AC24 AC23 AC22 AC12 AC10 AB9 AB7 AB2 AB19 AB10 AB1 AA4 AA16 AA13 AA11 A9 A7 A4 A26 A23 A21 A19 A15 A12 A1
D
C
B
ICH6_BGA609
C321 @ 0.1U_0402_16V4Z 1 2 C332 0.1U_0402_16V4Z 1 2
ICH6_BGA609
C307 0.01U_0402_16V7K 1 2
+1.5VS
V5REF[2] V5REF[1]
G16 G15 F16 F15 E16 D16 C16
1
C281 0.01U_0402_16V7K 1 2
+3VS
Near PIN U7
AB18 P7
PCI/IDE RBP
1
2
2
VCC2_5[4] VCC2_5[2]
VCCSATAPLL VCC3_3[22]
2
C296 0.1U_0402_16V4Z 1 2 C305 0.1U_0402_16V4Z 1 2
2 VCCSUS1_5[1]
ICH6_VCCPLL C271 0.01U_0402_16V7K
C263 0.1U_0402_16V4Z
+1.5VS
2
1
A17 B17 C17 F18 G17 G18
VCCSUS1_5[3] VCCSUS1_5[2]
U7 R7
2
Near PIN AG13, AG16
Near PIN A17
L11 CHB1608U301_0603 1 2
R184 1
1
2
0.1U_0402_16V4Z
C313
2
C316
+3VALW
0.1U_0402_16V4Z
Near PIN AE1
A11 U4 V1 V7 W2 Y7
SATA
AA6 AB4 AB5 AB6 AC4 AD4 AE4 AE5 AF5 AG5
+1.5VS
P1 M7 L7 L4 J7 H7 H1 E4 B1 A6
1
C346 0.1U_0402_16V4Z 1 2
+3VS
VSS[172] VSS[171] VSS[170] VSS[169] VSS[168] VSS[167] VSS[166] VSS[165] VSS[164] VSS[163] VSS[162] VSS[161] VSS[160] VSS[159] VSS[158] VSS[157] VSS[156] VSS[155] VSS[154] VSS[153] VSS[152] VSS[151] VSS[150] VSS[149] VSS[148] VSS[147] VSS[146] VSS[145] VSS[144] VSS[143] VSS[142] VSS[141] VSS[140] VSS[139] VSS[138] VSS[137] VSS[136] VSS[135] VSS[134] VSS[133] VSS[132] VSS[131] VSS[130] VSS[129] VSS[128] VSS[127] VSS[126] VSS[125] VSS[124] VSS[123] VSS[122] VSS[121] VSS[120] VSS[119] VSS[118] VSS[117] VSS[116] VSS[115] VSS[114] VSS[113] VSS[112] VSS[111] VSS[110] VSS[109] VSS[108] VSS[107] VSS[106] VSS[105] VSS[104] VSS[103] VSS[102] VSS[101] VSS[100] VSS[99] VSS[98] VSS[97] VSS[96] VSS[95] VSS[94] VSS[93] VSS[92] VSS[91] VSS[90] VSS[89] VSS[88] VSS[87]
+RTCVCC
C337 @ 0.1U_0402_16V4Z 1 2 C287 0.1U_0402_16V4Z 1 2
Near PIN A24
1
1
1
2
2
C353 0.1U_0402_16V4Z
2
VCC3_3[11] VCC3_3[10] VCC3_3[9] VCC3_3[8] VCC3_3[7] VCC3_3[6] VCC3_3[5] VCC3_3[4] VCC3_3[3] VCC3_3[2]
1
2
U9D E27 Y6 Y27 Y26 Y23 W7 W25 W24 W23 W1 V4 V27 V26 V23 U25 U24 U23 U15 U13 T7 T27 T26 T23 T16 T15 T14 T13 T12 T1 R4 R25 R24 R23 R17 R16 R15 R14 R13 R12 R11 P22 P16 P15 P14 P13 P12 N7 N17 N16 N15 N14 N13 N12 N11 N1 M4 M27 M26 M23 M16 M15 M14 M13 M12 L25 L24 L23 L15 L13 K7 K27 K26 K23 K1 J4 J25 J24 J23 H27 H26 H23 G9 G7 G21 G12 G1
GROUND
C
1
1
RB751V_SOD323
2
0.1U_0402_16V4Z
2
2 R212 10_0402_5%
AA10 AG19 AG16 AG13 AD17 AC15 AA17 AA15 AA14 AA12
C342 0.1U_0402_16V4Z
+3VALW D14
VCC3_3[21] VCC3_3[20] VCC3_3[19] VCC3_3[18] VCC3_3[17] VCC3_3[16] VCC3_3[15] VCC3_3[14] VCC3_3[13] VCC3_3[12]
C311 0.1U_0402_16V4Z
C312 @0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
+5VALW
1
C339 0.1U_0402_16V4Z 1 2
0.1U_0402_16V4Z C354
1
2
C309 0.1U_0402_16V4Z
PCIE
2
C310 1U_0603_10V4Z
C338
ICH_V5REF_RUN 2
C335 0.1U_0402_16V4Z 1 2
0.1U_0402_16V4Z C323
1
1
RB751V_SOD323
C334 0.1U_0402_16V4Z 1 2
0.1U_0402_16V4Z C360
R215 10_0402_5%
C330 0.1U_0402_16V4Z 1 2
C317
2
2
D15
C319 @ 0.1U_0402_16V4Z 1 2
C343
+3VS
+5VS
C270 C268 C277 1 1 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C325 @ 0.1U_0402_16V4Z 1 2
C294 0.1U_0402_16V4Z
2
220U_D2_4VM
F9 U17 U16 U14 U12 U11 T17 T11 P17 P11 M17 M11 L17 L16 L14 L12 L11 AA21 AA20 AA19
C308 0.1U_0402_16V4Z
C261 D
2
VCC1_5[98] VCC1_5[97] VCC1_5[96] VCC1_5[95] VCC1_5[94] VCC1_5[93] VCC1_5[92] VCC1_5[91] VCC1_5[90] VCC1_5[89] VCC1_5[88] VCC1_5[87] VCC1_5[86] VCC1_5[85] VCC1_5[84] VCC1_5[83] VCC1_5[82] VCC1_5[81] VCC1_5[80] VCC1_5[79]
CORE
+
2
VCC1_5[1] VCC1_5[2] VCC1_5[3] VCC1_5[4] VCC1_5[5] VCC1_5[6] VCC1_5[7] VCC1_5[8] VCC1_5[9] VCC1_5[10] VCC1_5[11] VCC1_5[12] VCC1_5[13] VCC1_5[14] VCC1_5[15] VCC1_5[16] VCC1_5[17] VCC1_5[18] VCC1_5[19] VCC1_5[20] VCC1_5[21] VCC1_5[22] VCC1_5[23] VCC1_5[24] VCC1_5[25] VCC1_5[26] VCC1_5[27] VCC1_5[28] VCC1_5[29] VCC1_5[30] VCC1_5[31] VCC1_5[32] VCC1_5[33] VCC1_5[34] VCC1_5[35] VCC1_5[36] VCC1_5[37] VCC1_5[38] VCC1_5[39] VCC1_5[40] VCC1_5[41] VCC1_5[42] VCC1_5[43] VCC1_5[44] VCC1_5[45]
IDE
2
U9E AA22 AA23 AA24 AA25 AB25 AB26 AB27 F25 F26 F27 G22 G23 G24 G25 H21 H22 J21 J22 K21 K22 L21 L22 M21 M22 N21 N22 N23 N24 N25 P21 P25 P26 P27 R21 R22 T21 T22 U21 U22 V21 V22 W21 W22 Y21 Y22
PCI
1
USB
2 +1.5VRUN_L
USB CORE
L10 0_0603_5% 1
+1.5VS
C322 @ 0.1U_0402_16V4Z 1 2
+1.5VS
C356 0.1U_0402_16V4Z
Near PIN F27(C968), P27(C949), AB27(C950)
A
Near PIN AG10 2
Compal Electronics, Inc. Title
Near PIN AC27
5
ICH6(4/4) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
3
2
Size
Document Number
Rev 0.1
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 1
22
of
46
B
C
D
HDD Connector
E
F
G
CD-ROM Connector
IDE_HDD[0..15] 20
C258
JP12 1
20 20
IDE_HDA1 IDE_HDA0
32
HDD_ACT# +5VS
29
R78
2 470_0402_5%
1
2 @ 10K_0402_5% PDIAG#
IDE_HDA2 IDE_HDCS3#
SIDE_RST#
+5VS
IDE_HDA2 20 +5VS
20
IDE_HIRQ
IDE_HDIOW# IDE_ HIORDY IDE_HIRQ IDE_HDA1 IDE_HDA0 SW_IDE_SDCS1# HDD_ACT#
R197 10K_0402_5%
R216
1
+5VMOD
4.7K_0402_5% 1
45
IDE_HDD7 IDE_HDD6 IDE_HDD5 IDE_HDD4 IDE_HDD3 IDE_HDD2 IDE_HDD1 IDE_HDD0
Pull down set primary
R79 @ 10K_0402_5%
2
47P_0402_50V8J JP21
2
C262 47P_0402_50V8J
1
1
CD_GND
+5VMOD R77
C266
2
47P_0402_50V8J
1
OCTEK_HDD-22EG1_ REVERS 46
INT_CD_L
2
IDE_HIORDY IDE_HDACK#
IDE_HDD8 IDE_HDD9 IDE_HDD10 IDE_HDD11 IDE_HDD12 IDE_HDD13 IDE_HDD14 IDE_HDD15
1
20 20
IDE_HDREQ IDE_HDIOW# HDIOR# IDE_ HIORDY IDE_HDACK# HD D_HIRQ IDE_HDA1 IDE_HDA0 IDE_HDCS1# HDD_ACT#
29
43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
2
IDE_HDREQ IDE_HDIOW#
43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
2
20 20
44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
46
1
44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
45
PIDE_RST# IDE_HDD7 IDE_HDD6 IDE_HDD5 IDE_HDD4 IDE_HDD3 IDE_HDD2 IDE_HDD1 IDE_HDD0
H
Pull high set slave SEC_CSEL
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
1
INT_CD_R 29
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
IDE_HDD8 IDE_HDD9 IDE_HDD10 IDE_HDD11 IDE_HDD12 IDE_HDD13 IDE_HDD14 IDE_HDD15 IDE_HDREQ IDE_HDIOR# IDE_HDACK# PDIAG# IDE_HDA2 SW_IDE_SDCS3#
+5VMOD
GND GND
A
Layout Note: W=80 mils
53 54
OCTEK_CDR-50TA1
2
2
+5VS
Placea caps. near HDD CONN. +5VMOD
+5VMOD Source
2
1 C318
2
6 5 2 1
4
1
2
10U_0805_10V4Z
80mil
+5VALW
S
Pls close HDD connector
1
1U_0603_10V4Z
Q25
C289
C306
C541 10U_0805_10V4Z
2
D
2
1
0.1U_0402_16V4Z
C124
C121
2
1
10U_0805_10V4Z
1
1U_0603_10V4Z
C123
2
0.1U_0402_16V4Z
1
Layout Note: Place close to CD-ROM CONN.
O
3
U16B
1 R412 2 0_0402_5%
B
1
EC_IDERST# 33
U34 O
4
NONDJ@
R366 10K_0402_5% SWDJ@ HDIOR#
S
D
R182 10K_0402_5% SWDJ@ SW_IDE_SDCS3#
O
2
I
OE#
IDE_HDCS3#
8
PLTRST_SWDJ#
+3VS
2
1
5 NONDJ@
OE#
P 3
G
I
20
IDE_HDCS3# 9
G_PCI_RST# D
2 G 3
SWDJ@ SN74LVC125APWLE_TSSOP14 EC_IDERST#
IDE_HDIOR#2
3
R198 10K_0402_5% SWDJ@
10 +3VALW
4
A
+3VALW
U17C
1 2 NONDJ@ 33_0402_5%
PIDE_RST#
+5VMOD
G_PCI_RST#
IDE_HRESET#
IDE_HDIOR#
6
HD D_HIRQ
1
NONDJ@
R175
20
O
2
G
I
3
Q43 SWDJ@ 2N7002_SOT23
SWDJ@ SN74LVC125APWLE_TSSOP14
R176 6 1 2 PIDE_RST# SWDJ@ 0_0402_5% SN74LVC08APW_TSSOP14 SWDJ@
P
5
2
IDE_HDCS1#
1
1
SWDJ@ SN74LVC08APW_TSSOP14
7
IDE_HDCS1#
O B
IDE_HIRQ R183 10K_0402_5% SWDJ@ SW_IDE_SDCS1#
1
G
B
A
7
5
O
10
21 IDE_HRESET#
4
8
P
14
14
20
OE#
U17B
C288 +3VALW SWDJ@ 0.1U_0402_16V4Z
U16C
R453 NONDJ@ 0_0402_5% 1 2
2 G
4
+3VALW
A
Q24 DTC124EK_SC59
+5VMOD
NONDJ@ 0_0402_5%
29,33 EC_IDERST
9
3
CD_PLAY 29,33
G_PCI_RST# R180
1
+5VMOD
PLTRST_SWDJ#
CD_PLAY
1
R189 10K_0402_5% SWDJ@
2
1
R191 10K_0402_5% SWDJ@
1
SWDJ@ SN74LVC08APW_TSSOP14
19 PLTRST_SWDJ#
1 2
SWDJ@ SN74LVC125APWLE_TSSOP14 7
2 7
1
1
14 I
C275 10U_0805_10V4Z
1
AOS3401_SOT23 +5VAMP
2
B
10K_0402_5% 1
SIDE_RST#
3
G
O
2
2
R222 2
1U_0603_10V4Z
U17A
P 3
OE#
14 P
U16A
G
IDE_DRESET#
21 IDE_DRESET#
3
A
C276 1 2
SWDJ_RST_HOLD 33
2
G
1
2
D
+3VALW SWDJ@ 0.1U_0402_16V4Z C284
Q23
S
3
G
+5VALW
+3VALW PLTRST_SWDJ#
+5VALW
SI3443DV_TSOP6
1 2 R223 330K_0402_5%
S
Q22 2N7002_SOT23 SWDJ@
4
1 R452 2 0_0402_5%
Compal Electronics, Inc.
SWDJ@ 74LVC1G125GW_SOT3535
Title
HDD & CD-ROM CONN. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 R195 2 0_0402_5% C
D
E
F
Size
Document Number
Rev 0.2
LA-2592 Date:
Tuesday, February 15, 2005 G
Sheet
23 H
of
46
5
4
3
2
1
+3VALW +3VALW C413 1U_0603_10V4Z
8110S@ 2SB1188_SC62 3
JP20
1 3 1
+1.8V_LAN
1 Q37
2SB1188_SC62 +2.5V_LAN Q35
2
CTRL25
CTRL18
2
2
1 1 D
C411 4.7U_0805_10V4Z
19,25,27,28 PCI_AD[0..31]
C462 8110S@ 4.7U_0805_10V4Z
R384 1
19,25,27,28 PCI_PAR 19,25,27,28 PCI_FRAME# 19,25,27,28 PCI_IRDY# 19,25,27,28 PCI_TRDY# 19,25,27,28 PCI_DEVSEL# 19,25,27,28 PCI_STOP#
PAR FRAME# IRDY# TRDY# DEVSEL# STOP#
19,25,27,28 PCI_PERR# 19,25,27,28 PCI_SERR#
70 75
PERR# SERR#
30 29
REQ# GNT#
25
INTA#
31
PME#
PCI_REQ0# PCI_GNT0#
19 PCI_PIRQF# 19,28,33 ICH_PME# 19,25,27,28,33 PCIRST# CLK_33M_LAN
18 CLK_33M_LAN 21,27,28,33 CLKRUN#
1
CLK_33M_LAN
R359 @ 10_0402_5%
117 115 114 113
27
RST#
28 65
CLK CLKRUN#
4 17 128
GND/VSS GND/VSS GND/VSS
21 38 51 66 81 91 101 119
GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST GND/VSSPST
A
GND GND GND GND
5 6 7 8
10 120
NC/HSDAC+ NC/HG NC/LG2 NC/LV2
11 123 124 126
6
PR2-
MDO2-
5
PR3-
MDO2+
4
PR3+
MDO1+
3
PR2+
MDO0-
2
PR1-
MDO0+
1
PR1+
D
SHLD2
9
SHLD1
10
0.1U_0402_16V4Z +3VALW
2
AT93C46-10SI-2.7_SO8 +2.5V_LAN U22
1
NC/AVDDH NC/HV
PR4+
MDO1-
DC234000B00 C457
NC/MDI2+ NC/MDI2NC/MDI3+ NC/MDI3-
88
7
1
14 15 18 19
NC/M66EN
C396 2
2
R337 R336 R350
C447 27P_0402_50V8J
C449 27P_0402_50V8J
2
C395
8110S@ 0.01U_0402_16V7K 2 1
C394 2
2 1K_0402_5% 2 15K_0402_5% 2 5.6K_0603_1%
1 1 1
8110S@ 0.01U_0402_16V7K 1
1
LAN_X1 LAN_X2
8110S@ 0.01U_0402_16V7K 1
+3VS C393
5.6K for 8100CL 2.49K for 8110S(B)
8110S@ 0.01U_0402_16V7K 2 1
TXD+/MDI0+ TXD-/MDI0-
12 11 10
TD4TD4+ TCT4
MX4MX4+ MCT4
13 14 15
MDO0+ MDO0MCT0
RXIN+/MDI1+ RXIN-/MDI1-
9 8 7
TD3TD3+ TCT3
MX3MX3+ MCT3
16 17 18
MDO1+ MDO1MCT1
NC/MDI2+ NC/MDI2-
6 5 4
TD2TD2+ TCT2
MX2MX2+ MCT2
19 20 21
MDO2+ MDO2-
NC/MDI3+ NC/MDI3-
3 2 1
TD1TD1+ TCT1
MX1MX1+ MCT1
22 23 24
MDO3+ MDO3-
C344 RJ45_GND2 2 1 R256 75_0402_5%
1
1000P_0402_50V7K 2 1 R260 75_0402_5% 2 1 R259 8110S@ 75_0402_5%
2 8110S@ 75_0402_5%
C
1 R257
8110S@ 0.5u_24HST1041A-2 8110S@ 0.1U_0402_16V4Z 1 R363 2 8110S@ 0_0805_5% +3VALW 1 1 C459 C461 8110S@ 0.1U_0402_16V4Z 0_0402_5% 1 2 2 8110S@
use 24ST1041A-4
AVDDH
2 R326
DVDD_A
1 1
NC/VSS NC/VSS
9 13
NC/GND NC/GND NC/GND NC/GND NC/GND NC/GND
22 48 62 73 112 118
CTRL25
8
CTRL25
RTT3/CRTL18
125
CTRL18
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
26 41 56 71 84 94 107
2
U21 TXD+/MDI0+ TXD-/MDI0-
+1.8V_LAN
C381 1
R351 8110S@ 0_0402_5%
2 8100C@ 0.1U_0402_16V4Z RXIN+/MDI1+ RXIN-/MDI1-
2 C430 8110S@ 0.1U_0402_16V4Z
8 7 6 5 4 3 2 1
TDTD+ CT NC NC CT RDRD+
TXTX+ CT NC NC CT RXRX+
MDO0+ MDO0MCT0
9 10 11 12 13 14 15 16
MCT1 MDO1+ MDO1-
8100C@ LF-H80P_16P
R317 8110S@ 49.9_0402_1% NC/MDI3+ 2 NC/MDI3-
2
1 C423 0.1U_0402_16V4Z
1 C488 0.1U_0402_16V4Z
2
2
1 C476 0.1U_0402_16V4Z
2
1 C486 0.1U_0402_16V4Z
2
C409 B
1 2
2
1
1
R316 8110S@ 49.9_0402_1% 8110S@ 0.01U_0402_16V7K
+3VALW 1
C442 0.1U_0402_16V4Z
R310 8110S@ 49.9_0402_1% NC/MDI2+ 2
C408 1 2
1 NC/MDI2- 2 1 R309 8110S@ 49.9_0402_1% 8110S@ 0.01U_0402_16V7K AVDDL
3 7 20 16
1
2
NC/VDD18 NC/VDD18 NC/VDD18 NC/VDD18 NC/VDD18
GND NC NC VCC
25MHZ_16P_XSL025000FK1H Y3 LAN_X1 2 LAN_X2 1
105 23 127 72 74
Power
2 C440 @ 10P_0402_50V8J
35 52 80 100
DO DI SK CS
PR4-
MDO3+
FOX_JM36113-P1063-7F
TXD+/MDI0+ TXD-/MDI0RXIN+/MDI1+ RXIN-/MDI1-
LWAKE ISOLATE# RTSET NC/SMBCLK NC/SMBDATA
VDD25/VDD18 VDD25/VDD18 VDD25/VDD18 VDD25/VDD18
4 3 2 1
8
+3VALW
1 2 5 6
121 122
AVDD33/AVDDL AVDD33/AVDDL AVDD33/AVDDL NC/AVDDL
2 3.6K_0402_5% U27
LAN_EEDO LAN_EEDI LAN_EECLK LAN_EECS
1 C426 0.1U_0402_16V4Z
R335 1
1 C424 0.1U_0402_16V4Z
2
2
C427 0.1U_0402_16V4Z DVDD
32 54 78 99
1
2
1
2
LED0 LED1 LED2 NC/LED3
X1 X2
LAN I/F
IDSEL
76 61 63 67 68 69
2 LAN_IDSEL 100_0402_5%
108 109 111 106
NC/MDI2+ NC/MDI2NC/MDI3+ NC/MDI3-
46
1 R364
EEDO AUX/EEDI EESK EECS
TXD+/MDI0+ TXD-/MDI0RXIN+/MDI1+ RXIN-/MDI1-
PCI I/F
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C/BE#0 C/BE#1 C/BE#2 C/BE#3
19 19
B
104 103 102 98 97 96 95 93 90 89 87 86 85 83 82 79 59 58 57 55 53 50 49 47 43 42 40 39 37 36 34 33 92 77 60 44
PCI_C_BE0# PCI_C_BE1# PCI_C_BE2# PCI_C_BE3#
PCI_AD17
2
PCI_AD[0..31]
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 19,25,27,28 19,25,27,28 19,25,27,28 19,25,27,28
2
C458 8110S@ 0.1U_0402_16V4Z
2
U25
C
1
MDO3-
24 45 64 110 116
1 C422 0.1U_0402_16V4Z
1 C489 0.1U_0402_16V4Z
2
2
1 C464 0.1U_0402_16V4Z
2
C487 0.1U_0402_16V4Z
2 8100C@ 0_0805_5%
+3VALW
8110S@ 0_0805_5% R328 1 2
+2.5V_LAN
R413 1
+1.8V_LAN
2 8110S@ 0_0805_5%
R334 1
8100C@ 0_0805_5% 2
R314 49.9_0402_1% TXD+/MDI0+ 2
2
C456
2
C466
2
C479
2
2
C451
8110S@ 0.1U_0402_16V4Z 1 1 1 1 8110S@ 0.1U_0402_16V4Z 8110S@ 0.1U_0402_16V4Z 8110S@ 0.1U_0402_16V4Z V_12P R315 1 2 +2.5V_LAN AVDD25/HSDAC- 12 8100C@ 0_0402_5% 1 C425 R307 AVDDH RTL8100CL_LQFP128 1 2 8110S@ 0_0402_5% 10/100 8100CL@-SA081000300(GM) 0.1U_0402_16V4Z R350-5.6K-SD014560100 2
2
TXD-/MDI0-
2 R313 49.9_0402_1%
R312 49.9_0402_1% RXIN+/MDI1+ 2
+2.5V_LAN
+1.8V_LAN C419
2 R311 49.9_0402_1%
1
1 0.01U_0402_16V7K
C406 1 2
RXIN-/MDI1-
8110S@ 0.1U_0402_16V4Z 1
C407 1
1
1 0.01U_0402_16V7K A
near LAN controller
GLAN 8110S@-SA081100100(PM) R350-2.49K-SD014249100
Compal Electronics, Inc. Title
LAN CONTROLLER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size
Document Number
Rev 0.2
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 1
24
of
46
A
B
C
D
E
+3VS 714@ 0.1U_0402_16V4Z
26 26
VCCD0# VCCD1#
+S1_VCC +3VS
C383
2 714@
1 C415
2
1 C437
C414
2
2 714@
0.1U_0402_16V4Z 0.1U_0402_16V4Z 714@ 0.1U_0402_16V4Z +3VS 714@ 0.1U_0402_16V4Z
1
1 C399
2 714@
1 C410
2
1 C436
C438
2
2 714@
0.1U_0402_16V4Z 0.1U_0402_16V4Z 714@ 0.1U_0402_16V4Z 2
19,24,27,28 19,24,27,28 19,24,27,28 19,24,27,28
PCI_C_BE3# PCI_C_BE2# PCI_C_BE1# PCI_C_BE0#
1
CLK_33M_CBS
19,24,27,28,33 PCIRST# 19,24,27,28 PCI_FRAME# 19,24,27,28 PCI_IRDY# 19,24,27,28 PCI_TRDY# 19,24,27,28 PCI_DEVSEL# 19,24,27,28 PCI_STOP# 19,24,27,28 PCI_PERR# 19,24,27,28 PCI_SERR# 19,24,27,28 PCI_PAR 19 PCI_REQ1# 19 PCI_GNT1# 18 CLK_33M_CBS
2
R301 @ 10_0402_5%
2
1
C384 @ 4.7P_0402_50V8C
+3VS
+SD_PULLHIGH
PCI_PIRQB#
4
1 R347 1 R325 1 R348 1 R318 1 R327
2 714@ 2 714@ 2 714@ 2 714@ 2 714@
2
G4 J4 K1 K3 L1 L2 L3 M1 M2 A1 B1 H1
PCIRST# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR PCIREQ# PCIGNT# PCICLK
L8 L11
RIOUT#_PME# SUSPEND#
26 SDCD# 26 SDWP 26 MS_XD_SD_PWREN#
26 SDCLK_XDWE# 26 SDCMD_XDALE 26 SDD0_XDD7 26 SDD1_XDD0 26 SDD2_XDCLE 26 SDD3_XDD4
F4 K8 N9 K9 N10 L10 N11 M11 J9
PLTRST_MCH# M10
B4 C8 D12 H11 L9 L6 N4 K2 G1 F3
IDSEL
CBS_CC/BE3# CBS_CC/BE2# CBS_CC/BE1# CBS_CC/BE0#
CRST#/RESET CFRAME#/A23 CIRDY#/A15 CTRDY#/A22 CDEVSEL#/A21 CSTOP#/A20 CPERR#/A14 CSERR#/WAIT# CPAR/A13 CREQ#/INPACK# CGNT#/WE# CCLK/A16
B9 B11 A12 A13 B13 C12 C13 A5 D13 B8 C11 B12
CBS_CRST# CBS_CFRAME# C BS_CIRDY# CBS_CTRDY# CBS_CDEVSEL# CBS_CSTOP# +S1_VCC CBS_CPERR# CBS_CSERR# CBS_CPAR CBS_CREQ# CBS_CGNT# R19 CBSCCLK 1 2 CBS_CCLK TI1410@ R358 714@ 33_0402_5% 43K_0402_5% CBS_CSTSCHNG CBS_CCLKRUN#
CBLOCK#/A19
MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 MFUNC7
SDCD# SDWP/SMWPD# SDPWREN33#
H5
SDCLKI
SPKROUT CAUDIO/BVD2_SPKR#
M9 B5
CCD2#/CD2# CCD1#/CD1# CVS2/VS2# CVS1/VS1 CRSV3/D2 CRSV2/A18 CRSV1/D14
GND_SD
A4 L12 D9 C6 A2 E10 J13
MSINS# MSPWREN#/SMPWREN# MSBS/SMDATA1 MSCLK/SMRE# MSDATA0/SMDATA2 MSDATA1/SMDATA6 MSDATA2/SMDATA5 MSDATA3/SMDATA3
H7 J8 H8 E9 G9 H9 G8 F9
SMBSY# SMCD# SMWP# SMCE#
H6 J7 J6 J5
SDCLK/SMWE# SDCMD/SMALE SDDAT0/SMDATA7 SDDAT1/SMDATA0 SDDAT2/SMCLE SDDAT3/SMDATA4
714@ CB714_LFBGA169
D11 CBS_CBLOCK# D6
SD/MMC/MS/SM VCC_SD
E8 F8 G7
C5 D5
CINT#/READY_IREQ#
GRST#
E7
G5
B7 A11 E11 H13
CSTSCHG/BVD1_STSCHG# CCLKRUN#/WP_IOIS16#
714@ 1 0.1U_0402_16V4Z
F6 1 R306 2 714@ 33_0402_5%E5 E6 F7 F5 G6
CCBE3#/REG# CCBE2#/A12 CCBE1#/A8 CCBE0#/CE1#
JP10 CBS_CAD0 CBS_CAD1 CBS_CAD3 CBS_CAD5 CBS_CAD7 CBS_CC/BE0# CBS_CAD9 CBS_CAD11 CBS_CAD12 CBS_CAD14 CBS_CC/BE1# CBS_CPAR CBS_CPERR# CBS_CGNT# CBS_CINT# +S1_VCC +S1_VPP
CBS_CCLK C BS_CIRDY# CBS_CC/BE2# CBS_CAD18 CBS_CAD20 CBS_CAD21 CBS_CAD22 CBS_CAD23 CBS_CAD24 CBS_CAD25 CBS_CAD26 CBS_CAD27 CBS_CAD29 CBS_RSVD/D2 CBS_CCLKRUN#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
GND GND D3 CD1# D4 D11 D5 D12 D6 D13 D7 D14 CE1# D15 A10 CE2# OE# VS1# A11 IORD# A9 IOWR# A8 A17 A13 A18 A14 A19 WE# A20 IREQ# A21 VCC VCC VPP1 VPP2 A16 A22 A15 A23 A12 A24 A7 A25 A6 VS2# A5 RESET A4 WAIT# A3 INPACK# A2 REG# A1 SPKR# A0 STSCHG# D0 D8 D1 D9 D2 D10 IOIS16# CD2# GND GND
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
69 70 71 72 73 74 75 76 77 78
GND GND GND GND GND GND GND GND GND GND
79 80 81 82 83 84 85 86 87 88
GND GND GND GND GND GND GND GND GND GND
CBS_CCD1# CBS_CAD2 CBS_CAD4 CBS_CAD6 CBS_RSVD/D14 CBS_CAD8 CBS_CAD10 CBS_CVS1 CBS_CAD13 CBS_CAD15 CBS_CAD16 CBS_RSVD/A18 CBS_CBLOCK# CBS_CSTOP# CBS_CDEVSEL# +S1_VCC +S1_VPP
CBS_CTRDY# CBS_CFRAME# CBS_CAD17 CBS_CAD19 CBS_CVS2 CBS_CRST# CBS_CSERR# CBS_CREQ# CBS_CC/BE3# CBS_CAUDIO CBS_CSTSCHNG CBS_CAD28 CBS_CAD30 CBS_CAD31 CBS_CCD2#
2
CBS_CINT#
FOXCONN_1CA4A501-TC-A2_LT 714@ 100K_0402_5% 2 1 R297
CBS_SPK# CBS_CAUDIO
CBS_CCD2#
+3VS
CBS_SPK# 29
CBS_CCD1# 3
@ CBS_CVS2 CBS_CVS1 CBS_RSVD/D2 CBS_RSVD/A18 CBS_RSVD/D14
MS_XD_SD_PWREN#
2
1
MS_INS# 26
MSBS_XDD1 1 2 R308 714@ 33_0402_5% MSD0_XDD2 MSD1_XDD6 MSD2_XDD5 MSD3_XDD3
XDWP#
@
XDBSY# XDCD# XDWP# XDCE#
2
1
270P_0402_50V7K
Chip has internal pull high
18 CLK_48M_CB
SDD0_XDD7 43K_0402_5% SDD1_XDD0 43K_0402_5% SDD3_XDD4 43K_0402_5% SDD2_XDCLE 43K_0402_5% SDCMD_XDALE 43K_0402_5%
PCIRST# PCI_FRAME# PCI _IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_PERR# PCI_SERR# PCI_PAR PCI_REQ1# PCI_GNT1#
CBS_CAD31 CBS_CAD30 CBS_CAD29 CBS_CAD28 CBS_CAD27 CBS_CAD26 CBS_CAD25 CBS_CAD24 CBS_CAD23 CBS_CAD22 CBS_CAD21 CBS_CAD20 CBS_CAD19 CBS_CAD18 CBS_CAD17 CBS_CAD16 CBS_CAD15 CBS_CAD14 CBS_CAD13 CBS_CAD12 CBS_CAD11 CBS_CAD10 CBS_CAD9 CBS_CAD8 CBS_CAD7 CBS_CAD6 CBS_CAD5 CBS_CAD4 CBS_CAD3 CBS_CAD2 CBS_CAD1 CBS_CAD0
C376
7,19,21,27 PLTRST_MCH#
+VCC_5IN1
+SD_PULLHIGH by BIOS setting
CBE3# CBE2# CBE1# CBE0#
B2 C3 B3 A3 C4 A6 D7 C7 A8 D8 A9 C9 A10 B10 D10 E12 F10 E13 F13 F11 G10 G11 G12 H12 H10 J11 J12 K13 J10 K10 K12 L13
270P_0402_50V7K
R132 TI1410@ 200_0402_5%
C439 2
+SD_PULLHIGH
E1 J3 N1 N5
CAD31/D10 CAD30/D9 CAD29/D1 CAD28/D8 CAD27/D0 CAD26/A0 CAD25/A1 CAD24/A2 CAD23/A3 CAD22/A4 CAD21/A5 CAD20/A6 CAD19/A25 CAD18/A7 CAD17/A24 CAD16/A17 CAD15/IOWR# CAD14/A9 CAD13/IORD# CAD12/A11 CAD11/OE# CAD10/CE2# CAD9/A10 CAD8/D15 CAD7/D7 CAD6/D13 CAD5/D6 CAD4/D12 CAD3/D5 CAD2/D11 CAD1/D4 CAD0/D3
C441
2
19
1
1
3
SMCD# 1 2 R298 714@ 43K_0402_5%
PCI_PIRQA#
21,33 SIRQ
SMCD# R131 TI1410@ 200_0402_5%
PCI_C_BE3# PCI_C_BE2# PCI_C_BE1# PCI_C_BE0#
1 2 R296 714@ 10K_0402_5% PCI_AD20 1 CBS_IDSEL 2 R303 714@ 100_0402_5% 19 cardbus
+3VS
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
1
1 C401
C2 C1 D4 D2 D1 E4 E3 E2 F2 F1 G2 G3 H3 H4 J1 J2 N2 M3 N3 K4 M4 K5 L5 M5 K6 M6 N6 M7 N7 L7 K7 N8
2
1
PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0
1
Closed to Pin L12 Closed to Pin A4
26 MSCLK_XDRE# 26 26 26 26 26
26 26 26 26
XDWP#
1 2 R299 714@ 2.2K_0402_5%
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
19,24,27,28 PCI_AD[0..31]
714@ 0.1U_0402_16V4Z
CARDBUS
+S1_VCC
VCC10 VCC9 VCC8 VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 VCC1
VCCD1# VCCD0#
U23
1
VCCA2 VCCA1
714@
0.1U_0402_16V4Z 0.1U_0402_16V4Z
[email protected]_0402_16V4Z
A7 G13
2
D3 H2 L4 M8 K11 F12 C10 B6
2
M12 N12
2
1 C378
VPPD1 VPPD0
2 714@
1 C397
PCI Interface
1 C379
VPPD0 VPPD1
M13 N13
1
26 26
Close to 5 in 1 socket
CB714-B0-SA007140B10(PM) CB712-A0-SA007120000(GM) CB1410-B0-SA014100300 PCI1410A-SA014100030
4
Compal Electronics, Inc. Title
CardBus CTRL CB714
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Size
Document Number
Rev 0.2
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 E
25
of
46
+S1_VCC
12V
13 12 11
2 2 +S1_VPP
+5VS 714@ C418 0.1U_0402_16V4Z 1 2 714@ 1 2 4.7U_0805_10V4Z C421
3.3V 3.3V
U35
C373 714@ 1 0.1U_0402_16V4Z 1 714@ 4.7U_0805_10V4Z C370
OC
VCCD0# VCCD1# VPPD0 VPPD1
1 2 3 4
1
C387
25 25 25 25
2
GND IN IN EN#
OUT OUT OUT FLG
R300 714@ G528_SO8 714@ 10K_0402_5%
8 7 6 5 1
1
C374
C375
1
C560
@ 4.7U_0805_10V4Z 2 2 714@ 0.1U_0402_16V4Z 0.01U_0402_16V7K 714@ 2
25 MS_XD_SD_PWREN#
8
CP2211D3_SSOP16
2
7
714@ R295 10K_0402_5%
SHDN
C420
GND
3 4
2 2
+VCC_5IN1 +3VS
714@ 0.1U_0402_16V4Z
+3VS
2 2
VCCD0 VCCD1 VPPD0 VPPD1
1 2 15 14
16
C417
10
5V 5V
1
714@ 0.1U_0402_16V4Z 1 714@ 1 4.7U_0805_10V4Z
5 6
VPP
C372 714@ 1 0.1U_0402_16V4Z 1 714@ 4.7U_0805_10V4Z C369
1
9
VCC VCC VCC
2
U24
Close to 5 in 1 Connector
1
MSCLK_XDRE# 1
SDCLK_XDWE#
JP11
+VCC_5IN1
1 2 C400 714@ 0.1U_0402_16V4Z
C398 714@ 0.1U_0402_16V4Z 1 2 25 +VCC_5IN1
SDD0_XDD7 SDD1_XDD0 SDD2_XDCLE SDD3_XDD4 SDCLK_XDWE# SDCMD_XDALE
MSBS_XDD1 MSD0_XDD2 MSD1_XDD6 MSD2_XDD5 MSD3_XDD3 MS_INS#
MSCLK_XDRE#
41 40 22 21 39 37 23 31 26 29 34 42 43
SD_WP SD_CD SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 SD_GND SD_GND SD_CLK SD_VCC SD_CMD SD_CD-GND SD_WP-GND
24 25 28 27 30 33 32 35 36 38
MS_GND MS_BS MS_DATA0 MS_DATA1 MS_DATA2 MS_DATA3 MS_INS MS_SCLK MS_VCC MS_GND
XD_GND XD_R/B XD_RE XD_CE XD_CLE XD_ALE XD_WE XD_WP-IN XD_GND XD_DO XD_D1 XD_D2 XD_D3 XD_D4 XD_D5 XD_D6 XD_D7 XD_VCC XD_CD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
NC
20
TAITWUN_R007-620-L3
XDBSY# 25 MSCLK_XDRE# 25 XDCE# 25 SDD2_XDCLE 25 SDCMD_XDALE 25 SDCLK_XDWE# 25 XDWP# 25 SDD1_XDD0 25 MSBS_XDD1 25 MSD0_XDD2 25 MSD3_XDD3 25 SDD3_XDD4 25 MSD2_XDD5 25 MSD1_XDD6 25 SDD0_XDD7 25 +VCC_5IN1 XDCD# 25
R324 @ 0_0402_5%
R304 @ 0_0402_5% 2
SDWP SDCD#
2
25 25
1
1
C416 @ 10P_0402_50V8J 2
C385 @ 10P_0402_50V8J 2
Close to 5 in 1 Connector +VCC_5IN1 1 R302 1 R305 1 R450 1 R449
2 MSCLK_XDRE# 714@ 10K_0402_5% 2 SDCLK_XDWE# 714@ 10K_0402_5% XDCE# 2 714@ 2.2K_0402_5% XDBSY# 2 714@ 10K_0402_5%
Compal Electronics, Inc. Title
CARD BUS SOCKET THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Document Number
Rev 0.3
LA-2592 Date:
Tuesday, February 15, 2005
Sheet
26
of
46
5
4
3
2
+3VS
+3VS
2 R362
1 10K_0402_5%
R435 1 2 3 4
+3VS D
1
1
2
8 7 6 5
C505 0.1U_0402_16V4Z
1
2
1
C499 0.1U_0402_16V4Z
2
1
C504 0.1U_0402_16V4Z
2
1
C491 0.1U_0402_16V4Z
2
1
C498 0.1U_0402_16V4Z
2
1
C482 0.1U_0402_16V4Z
2
C467 0.1U_0402_16V4Z
1
2
C453 0.1U_0402_16V4Z D
+3VS
87
86 96 10 11 CYCLEOUT/CARDBUS CNA TEST17 TEST16
R0
OSCILLATOR
118
R1
119
X0
6
1 2 R404 6.34K_0402_1%
R430
G_RST GPIO3 GPIO2
2 1
C500
@ 10P_0402_50V8J 2
1 C515
0.01U_0402_16V7K
2 22P_0402_50V8J
FILTER0 FILTER1
30ppm
1 C507
92
SDA_1394
91
SCL_1394
PC0 PC1 PC2
99 98 97
TPBIAS0 TPA0+ TPA0TPB0 + TPB0 -
116 115 114 113 112
TEST9 TEST8
94 95
TEST3 TEST2 TEST1 TEST0
101 102 104 105
2 22P_0402_50V8J
R387 56.2_0402_1% XTPBIAS0 XTPA0+ XTPA0XTPB0+ XTPB0-
1
1
5 3
SCL
PHY PORT 1
R388 56.2_0402_1%
2
C484 1U_0603_10V4Z
XTPA0+ XTPA0XTPB0+ XTPB0-
32 32 32 32 B
EEPROM cancel, need System Support
R372 56.2_0402_1%
R373 56.2_0402_1%
C465
1
R370
TSB43AB21A_PQFP128 220P_0402_25V8K
5.11K_0402_1%
2
The connector depend on defferent project
Close Chip 1 0.1U_0402_16V4Z
Entry S3
+3VS
2
X1
4
POWER CLASS
** GPIO2 and GPIO3 defaults as an input and if it is not implemented, it is recommended that it be pulled low to ground with a 220 ohm resistor.
Power on
1000P_0402_50V7K
C
EEPROM 2 WIRE BUS SDA
8 9 109 110 111 117 126 127 128 17 23 30 33 44 55 64 68 75 83 93 103
220_1206_8P4R_5% @ 10_0402_5%
C485
1
SCL_1394 SDA_1394
14 89 90
2
C503
2
8 7 6 5
1000P_0402_50V7K
2
1
1 2 3 4
2
1
C470
Near 1394 IC
1 2 C502 0.1U_0402_16V4Z
FILTER
PLLGND1 REG_EN AGND AGND AGND AGND AGND AGND AGND DGND DGND REG18 DGND DGND DGND DGND DGND DGND DGND REG18 DGND
R360
CLK_33M_1394
1000P_0402_50V7K
X2 24.576MHz_16P_3XG-24576-43E1
B
7,19,21,25 PLTRST_MCH#
2
2
1
C463
2 1K_0402_5%
1
PCI BUS INTERFACE
CYCLEIN
BIAS CURRENT
1 R369
1
1000P_0402_50V7K
1
19,24,25,28 PCI_SERR# 19,24,25,28 PCI_PAR 21,24,28,33 CLKRUN# 19,24,25,28,33 PCIRST#
NC/(TPBIAS1) NC/(TPA1+) NC/(TPA1-) NC/(TPB1+) NC/(TPB1-)
125 124 123 122 121
2 4.7U_0805_10V4Z
L18 BLM21A601SPT_0805 1 2
2
1
C452
2
ID: AD16
2 100_0402_5%
106
+PLLVDD 1 C513
1000P_0402_50V7K
1
PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_PERR# PCI_PIRQE#
PCI_AD16 1 R414
CPS
TSB43AB21A /(TSB43AB22)
2
1
C454
2
19,24,25,28 19,24,25,28 19,24,25,28 19,24,25,28 19,24,25,28 19,24,25,28 19
CLK_33M_1394
1 15 27 39 51 59 72 88 100 7 1 2 107 108 120
1
PCI_C_BE3# PCI_C_BE2# PCI_C_BE1# PCI_C_BE0# CLK_33M_1394 PCI_GNT2# PCI_REQ2#
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE3 PCI_C/BE2 PCI_C/BE1 PCI_C/BE0 PCI_CLK PCI_GNT PCI_REQ PCI_IDSEL PCI_FRAME PCI_IRDY PCI_TRDY PCI_DEVSEL PCI_STOP PCI_PERR PCI_INTA/CINT PCI_PME/CSTSCHG PCI_SERR PCI_PAR PCI_CLKRUN PCI_RST
+3VS DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD PLLVDD AVDD AVDD AVDD AVDD AVDD
2
19,24,25,28 19,24,25,28 19,24,25,28 19,24,25,28 18 19 19
84 82 81 80 79 77 76 74 71 70 69 67 66 65 63 61 46 45 43 42 41 40 38 37 32 31 29 28 26 25 24 22 34 47 60 73 16 18 19 36 49 50 52 53 54 56 13 21 57 58 12 85
VDDP VDDP VDDP VDDP VDDP
U30
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
C
20 35 48 62 78
4.7K_1206_8P4R_5% PCI_AD[0..31]
19,24,25,28 PCI_AD[0..31]
S3 Wake-up
C506
2
1
2
C455 0.1U_0402_16V4Z
CLOSE CHIP
VCC(+3VS)
T1:
>2ms
PLTRST_MCH#
T1 A
T1 A
Note: GLOAB_RESET# Can Connect to PCI_PCIRST#
Compal Electronics, Inc. Title
IEEE 1394 CONTROLLER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size
Document Number
Rev 0.2
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 1
27
of
46
5
4
3
2
+3VS
1
+3VS
JP23 1
17
BT_LED
BT_LED
2 1
D
WL_BT_LED 32
3 1
17,33 WL/BT_ON C Q7
1N4148_SOT23
1 R43 2 2 B 1K_0402_5% R44
3
PCI_PIRQH#
CLK_33M_MPCI
18 CLK_33M_MPCI
10K_0402_5%
19
PCI_REQ3#
PCI_REQ3#
2
1 WLAN_ACT1
19
MMBT3904_SOT23 E
3
1
1N4148_SOT23
WLAN_ACT1 WL/BT_ON 1 WL_ON 2 D9 RB751V_SOD323 PCI_PIRQH#
PCI_AD31 PCI_AD29
2
PCI_AD27 PCI_AD25
CLK_33M_MPCI 2
D8
PCI_C_BE3# PCI_AD23
19,24,25,27 PCI_C_BE3#
R73 @ 10_0402_5% 1
PCI_AD21 PCI_AD19
2
1
C118 @4.7P_0402_50V8C
PCI_AD17 PCI_C_BE2# PCI _IRDY#
19,24,25,27 PCI_C_BE2# 19,24,25,27 PCI_IRDY#
CLKRUN# PCI_SERR#
21,24,27,33 CLKRUN# 19,24,25,27 PCI_SERR#
PCI_PERR# PCI_C_BE1# PCI_AD14
19,24,25,27 PCI_PERR# 19,24,25,27 PCI_C_BE1# C
PCI_AD12 PCI_AD10 PCI_AD8 PCI_AD7 PCI_AD5 PCI_AD3 +5VS
PCI_AD1
+5VS 2
C119
1 KEY 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123
2 KEY 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124
2
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125
125
126
126
GND GND
PCI_AD[0..31] 19,24,25,27 D3
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124
0.1U_0402_16V4Z
+5VS
PCI_PIRQG#
PCI_PIRQG# 19 +3VALW
PCIRST#
PCIRST#
PCI_GNT3#
19,24,25,27,33
2
PCI_GNT3# 19
ICH_PME#
ICH_PME# 19,24,33
2
C365 0.1U_0402_16V4Z
1
C110 0.1U_0402_16V4Z
1
PCI_AD30 PCI_AD28 PCI_AD26 PCI_AD24 MINIDSEL
1
PCI_AD22 PCI_AD20 PCI_PAR PCI_AD18 PCI_AD16
2
PCI_AD18
R293 100_0402_5% PCI_PAR 19,24,25,27
PCI_FRAME# PCI_TRDY# PCI_STOP#
PCI_FRAME# 19,24,25,27 PCI_TRDY# 19,24,25,27 PCI_STOP# 19,24,25,27
PCI_DEVSEL#
PCI_DEVSEL# 19,24,25,27
PCI_AD15 PCI_AD13 PCI_AD11
C
PCI_AD9 PCI_C_BE0#
PCI_C_BE0# 19,24,25,27
PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0
+3VALW 2
127 128
AMP_1318916-1 1
D
C364 0.1U_0402_16V4Z
1 B
B
+3VS
2
1
C371 0.047U_0402_16V4Z
2
1
C367 0.047U_0402_16V4Z
2
1
C111 0.047U_0402_16V4Z
2
1
C402 0.047U_0402_16V4Z
2
1
C112 0.047U_0402_16V4Z
2
1
C404 0.047U_0402_16V4Z
2
1
2
C368 0.047U_0402_16V4Z
1
C403 0.047U_0402_16V4Z
A
A
Compal Electronics, Inc. Title
MINIPCI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size
Document Number
Rev 0.1
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 1
28
of
46
A
B
C
D
E
1
+AVDD_AC97
R276 R242 10K_0402_1% 2
1
1
2
2.4K_0402_5% C329 1 2 MONO_INR
MONO_IN
1
Adjustable Output
+5VALW
1U_0603_10V4Z
+VDDA
1 2 560_0402_5%
SPKR
ERROR
5 6
CNOISE
1
GND
3
+VDDA
8
SD
R397 69.8K_0603_1%
SI9182DH-AD_MSOP8
MMBT3904_SOT23
1
C472
R396 24K_0402_1%
CD_PLAY
2
23,33
C468
3
E
1 2 R371 10K_0402_5%
4.7U_0805_10V4Z
2 7
VOUT SENSE or ADJ
1
3
1 2 B
DELAY
C490
21
MMBT3904_SOT23 E
CQ28
R282
C471
VIN
2
0.1U_0402_16V4Z
CBS_SPK#
2 B
MMBT3904_SOT23 E
CQ26
R232 1 2 560_0402_5%
0.1U_0402_16V4Z
2 B
4
3
25
1 2 560_0402_5%
BEEP#
1
33
4.7U_0805_10V4Z
1
U29 CQ27
R230
+3VS
AC97 Codec
2 R406
HP_OUT_R BIT_CLK
11
RESET#
10
SYNC
SDA XTLSEL
47
SPDIFI/EAPD
48
SPDIFO
2 D
S
IAC_SDATAI0 20
2
CD_GND To CD_GNDA Bypass 3
R432
3
AFILT1
29
AFILT1 C518 1000P_0402_50V7K
AFILT2
30
AFILT2 C514 1000P_0402_50V7K
VREFOUT
28
VREF
27
DCVOL
32
X3 24.576MHz_16P_3XG-24576-43E1 1 2 1 C512 2
+AVDD_AC97 1
22P_0402_50V8J 2
C501
DVSS1 DVSS2
31 33 34 43 44
NC AVSS1 AVSS2
40 26 42
CD_GND
R81
22P_0402_50V8J
**
@ 1M_0402_5%
+AUD_VREF
20K_0402_1% CD_GNDA 1
R445
R448
0_0402_5%
6.8K_0402_5%
VREF1 DCVOL REF2
NC VREFOUT2 VAUX DISABLE# SCK
23
R447 2
1
@ 1M_0402_5% XTL_OUT
SDATA_OUT
45 46
2 22_0402_5%
VAUX SMB_CLK
1 R424
1 2 +AVDD_AC97 R434 SWDJ@ 0_0603_5% 2 EC_IDERST 23,33 0_0402_5%
1
@
1
C520
0.1U_0402_16V4Z C521
2
2
@
1
ALC250-VD_LQFP48
2
1
+AUD_VREF
Analog Reference V
4.7U_0805_10V4Z
PC_BEEP
1 R437
2
PHONE
12
AC_SDATAI0
1
MIC2
13
SMB_DATA
2
22
3
1
MIC1
4 7
R428 @ 0_0402_5%
2
1
2
21
5
8
XTL_IN
R441 6.8K_0402_5%
Q40 @ 2N7002_SOT23 1 2 R386 0_0402_5%
1U_0603_10V4Z
CD_GND
20,30
6
SDATA_IN CD_R
19
15,33 SMB_EC_DA2 BITCLK
0.1U_0402_16V4Z
CD_L
2 BITCLK 22_0402_5%
R442 6.8K_0402_5%
@ 4.7K_0402_5%
C523
LINE_IN_R
18
1 R436
1U_0603_10V4Z
24
2
20,30 IAC_SDATO
LINE_IN_L
1 2 C516 27P_0402_50V8J AC_BITCLK
CD_L 1 2 C538 1U_0603_10V4Z CD_R 1 2 C528 1U_0603_10V4Z
1
39 41
R402 3.3K_0402_5%
1
37
HP_OUT_L
INTCD_L 1 20K_0402_1% INTCD_R 1 20K_0402_1%
2 R444 2 R443
2
MONO_OUT/VREFOUT3
JD1
INT_CD_R
2
JD2
17
INT_CD_L
23
R403
@ 1K_0402_5%
LINE_OUTR 31
23
1
16
R405
LINE_OUTL 31
2 1 G
LINER
LINE_OUTL 2 1U_0603_10V4Z LINE_OUTR 2 1U_0603_10V4Z
1 C508 1 C495
C517
20,30 IAC_SYNC
AC_RST# 1 2 R431 22_0402_5% AC _SYNC 1 2 R427 22_0402_5% AC_SDATO 1 2 R423 22_0402_5% SMB_DATA
9 36
20
IAC_RST#
1
LINE_OUT_R
CD_R 1 2 CD_AGND C539 1U_0603_10V4Z C_MIC 1 2 C531 1U_0603_10V4Z 1 2 C533 @ 1U_0603_10V4Z 1 2 C522 0.1U_0402_16V4Z MONO_INR
DVDD1
AUX_R
23
CD_GNDA
DVDD2
38
25
15
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z CD_L
MIC
20,30
LINEL
0.01U_0402_16V7K
31
35
C492
+AUD_VREF
LINE_OUT_L
1
R438 2.2K_0402_5% 1 2
AUX_L
@ 2N7002_SOT23 2 1.74K_0402_1%
2
3
C509 @ 1000P_0402_50V7K
14
Audio Signal Bias Circuit SMB_CLK
3
Q41 1 R374
C497 @ 1000P_0402_50V7K
1
1 2 C534 1U_0603_10V4Z 1 2 C535 1U_0603_10V4Z
AVDD2
AVDD1
U31
1
15,33 SMB_EC_CK2
1
C525 10U_0805_10V4Z
2
2
2
S
0.1U_0402_16V4Z
2 1 G
1
C526
D
1 C493
2
C494
@ 4.7K_0402_5% 2
@ 1K_0402_5%
0.1U_0402_16V4Z
1 C532 1 C529
2
R407
10U_0805_10V4Z
0_0402_5%
+VDDA
CHB2012U170_0805 2
R433
L16 1
C524
2
1
+AVDD_AC97
GND 4
GND To GNDA Bypass
GNDA
JOPEN3
WITH 14.318MHz : Rxxx POP WITH 24.576MHz : Rxxx DEPOP
JOPEN4
1 1
SHORT PADS 2 SHORT PADS 2
GND
4
GNDA
Compal Electronics, Inc. Title
Codec ALC250 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Size
Document Number
Rev 0.2
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 E
29
of
46
A
20,29
B
BITCLK
20 IAC_SDATAI1 20,29 IAC_SDATO 20,29 IAC_SYNC 20,29 IAC_RST#
C
D
E
BITCLK IAC_SDATAI1 1 IAC_SDATO R417 1 IAC _SYNC R422 1 IAC_RST# R426 1 R429
SV92A2 Codec ID Selection Table
SDATA_IN 2 SDATA_OUT 22_0402_5% 2 22_0402_5% S YNC 2 RESETN 22_0402_5% 2 22_0402_5% +3VALW ATP1 TP 1
S YNC SDATA_IN RESETN
2 4 6 8 10 12
2 4 6 8 10 12
13
MT1 MT2
14
AC12
+3VALW
+ AC11 1U_1206_25V
ATP2 TP 1
BITCLK
ATP8 TP 1 ATP3
1
BITCLK
AR14
AR12 10K_0402_5% N10124604
100_0402_5% N10118093
1
ATP4
MTG_HOLE
ATP5
Agere Systems Proprietary DRAFT COPY - FOR REVIEW ONLY SUBJECT TO CHANGE
AM2
1
SDATA_IN
1
SDATA_OUT
1
S YNC
1
RESETN
0
Output on: SDATA_IN0
Secondary Line 1
0
0
SDATA_IN0
Secondary Line 1
1
1
SDATA_IN1
Secondary Line 2
0
1
SDATA_IN1 4
Operates as Seocndary, line 1 modem in AC-97 systems and when populated with SV92A2 device based on internal pull ups on ID pins.
MDC15MOTHER AM1
ID0
1
0.1U_0402_16V4Z
2
SDATA_OUT 4
1 3 5 7 9 11
1
AJP2 1 3 5 7 9 11
ID1 Primary Line 1
AU1 1 2 3 4 5 6 7 8
MCLK/XIN GPIO_A/EE_SD/ID0 XOUT GPIO_B/EE_SC/RID BIT_CLK SDATA_IN1 VDD VA SDATA_IN0 GND SDATA_OUT AOUT/ID1 SYNC C1A RESET C2A
16 15 14 13 12 11 10 9
N10176139 AR13 4.7K_0402_5% N10125771 C1A C2A
SV92A2_REV E ATP6
1
ATP7
MTG_HOLE
AC13 0.1U_0402_16V4Z
No Ground Plane In DAA Section 3
3
AR10 536 ?%
AQ1 N7546657
N7514346
N7514408 N7514368
AR2 AQ5 N7547703 150_0402_5%
1.07K ?%
C1A
N7514352 N7546318 N7546063 N7545626 N7545741 N7545682
AFB3 N10187852
33pF AC2 C2A
AFB4
N7544958
N10187879
AC5 AR9
0.1U_0402_16V4Z
1 2 3 4 5 6 7 8
QE DCT RX IB C1B C2B VREG RNG1
AR5
DCT2 IGND DCT3 QB QE2 SC VREG2 RNG2
16 15 14 13 12 11 10 9
CSP1038
100K_0402_5%AQ2
NOTE: Ample copper pad should be dedicated to Q1, Q3, Q4, Q5, R1, R4, and R11. Please refer to the design advisory and layout guidelines for further details.
AC10
AR4 N7514356
AR1
AU2 AC1
AQ4
2.49K ?%
N7514376 N7547514 N7546878 N7546986
0.01uF AR6 100K_0402_5% AQ3
N7545016
2
AC4 0.47uF 50 V
AR11 73.2 ?%
N10233409
AR3 3.65K ?%
AC6
AC7
0.1U_0402_16V4Z
2.7nF
AZ1
33pF 2
2
43 V SC4TLZ43000
1
1M ?%
AC3 10nF AR8
AFB2
N7514330
N7514364
N7514358
20M
Ferrite Bead AD2 AC9
DNP FUSE
1000 pF
2
1
3
GSD2004S 1
ARV1 P3100SB
AF1 3
2
AF1_AJP1
4 IGND
2
GSD2004S
MTG 1 2 MTG
CSP1038A Line Side DAA Agere Systems Proprietary DRAFT COPY - FOR REVIEW ONLY SUBJECT TO CHANGE
AC8
3
1
AJP1 JAE
1000 pF
AD1 AR7 N7545577
AFB1 N7514386
N7514328
20M
Ferrite Bead
1
1
IGND
Compal Electronics, Inc. Title
MODEM-AgereMOM CPS1038 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
B
C
D
Rev 0.3
LA-2592 Date:
A
Document Number Sheet
Tuesday, February 15, 2005 E
30
of
46
A
B
C
D
E
+5VAMP +VDDA R454 @ 0_0805_5% 1 2 1
L17 +5V_AMP 1 2 CHB2012U170_0805 1 C496
0.1U_0402_16V4Z
2
2
1
D17 PSOT24C_SOT23
For EMI
2
0.1U_0402_16V4Z
R425 100K_0402_5%
SPKR+ SPKR-
U32
29 29
LINE_OUTL LINE_OUTR
17 2
TPA0232PWP_TSSOP24 1
2
1 12 13 24
EC_MUTE# 33
C127 1U_0603_10V4Z 1
For EMI
3
JACK_PLUG BEEP_AMP BYPASS_AMP SPKLSPKR-
C388
D16 PSOT24C_SOT23
1
1
1
C389
C390
1
1 2 C391
JP27
@ 47P_0402_50V8J @ 47P_0402_50V8J @ 47P_0402_50V8J 2 2 2 2 For @ 47P_0402_50V8J
2
2
1
1
C122
EMI
D18 PSOT24C_SOT23
0.47U_0603_16V7K
For EMI JP29
1 2 1
C557 2 2 1U_0603_10V4Z C556 1U_0603_10V4Z
2 1
ACES_20342-0239 C558 220P_0402_25V8K
C510 0.047U_0402_16V4Z
2
1
1
2
JP28 2 1
29
MIC
JP13
0.1U_0402_16V4Z 5
JOPEN5 INT_MIC 1
2
C559 ACES_88231-0200
MIC2
1
SHORT PADS 2
4
MIC IN
3 6 2 1
INTMIC
2 L19 FBM-11-160808-601-T_0603
7 8
C530 47P_0402_50V8J
C125 R439 100U_D2_6.3VM SPKR+_C 1 1 2 2 470_0402_5%
JOPEN6 SHORT PADS 1 2
2
JP14 INTSPK_CR+1 2 L20 FBM-11-160808-601-T_0603
+
SPKR+ 3
PR
5
JACK_PLUG
1
1 FM1
1
1 FM2
1
CF7 1
CF6 1
CF8 1
CF13 1
CF10 1
SPKL+
CF14 1
FM3 1
C519 100U_D2_6.3VM R80 SPKL+_C 1 1 2 2 470_0402_5% R82
INTSPK_CL+1 2 L4 FBM-11-160808-601-T_0603
1
CF12
CF5 1
1
CF9
CF4 1
R440 C527 47P_0402_50V8J
1K_0402_5% FM4
2
CF11
CF3 1
1
2
CF2 1
3
4
+
CF1
For EMI
FOX_JA6033L-1S1
1
1
ACES_85204-0200
SP020018900(2P)
1
2 3 4 21 5 23 6 20
SPKL+ SPKR+
22 15 14 11 9 16 10 8
3
0.01U_0402_16V7K 33 VOLUME_CTRL
PVDD SHUTDOWN# PVDD SE/BTL# VDD PC-BEEP BYPASS HP/LINE# LOUTVOLUME ROUTLOUT+ LIN ROUT+ RIN LLINEIN RLINEIN GND LHPIN GND RHPIN GND GND CLK
1
7 18 19
C536 2 1
ACES_85204-0200
1 2
2
1 2 100K_0402_5%
JP24
SPKL+ SPKL-
2
R446
3
2
C537
2
10U_0805_10V4Z
1 C561 @ 10U_0805_10V4Z
1 C511
2
1
1
1
1K_0402_5%
3 6 2 1
PL
1
1
2
2
7 8 FOX_JA6033L-1S1
C126 47P_0402_50V8J
Tune headphone volume
1
1
H2 HOLEA
H16 HOLEA
H12 HOLEA
1
H20 HOLEA
H3 HOLEA
1
1
1 H19 HOLEA
H21 HOLEA
1
H18 HOLEA
H1 HOLEA
1
H15 HOLEA
1
1
1 H6 HOLEA
H14 HOLEA
1
H8 HOLEA
H13 HOLEA
1
H7 HOLEA
H10 HOLEA
1
1
1
H9 HOLEA
1
1
H5 HOLEA
H11 HOLEA
1
1
H4 HOLEA
4
4
1
H17 HOLEA
Compal Electronics, Inc. Title
AMP & Audio Jack THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Size Custom Date:
Document Number
Rev 0.2
LA-2592 Sheet
Tuesday, February 15, 2005 E
31
of
46
A
B
C
D
USB Port
E
+USB_VCCA
1 C377 + @ 100U_6.3V_M
C392 2
1
1
2
2
C386 1000P_0402_50V7K
0.1U_0402_16V4Z +5VS
JP26
GND IN IN EN#
OUT OUT OUT FLG
2
5 6 7 8
GND1 GND2 GND3 GND4
For EMI
33 CAMERA_ONOFF#
OVCUR#3 21
G528_SO8
1
JP1
CAMERA_ONOFF# 21 USBP7+ 21 USBP7-
+5VS_CAM USBP7+ USBP7-
1 2 3 4 5
ACES_88266-0500
1 C357 +
C445 @ 1000P_0402_50V7K
100U_6.3V_M
2
1
Camera USB KEY
Q45 1
CAMERA@3 SI2301BDS_SOT23
SUYIN_020173MR004G552ZR
+USB_VCCA
SHORT PADS 2
2
C446 0.1U_0402_16V4Z 2 1 35 SYSON#
R365 10K_0402_5%
8 7 6 5
2
C412 @10P_0402_50V8J
1
U26 1 2 3 SYSON# 4
1
JOPEN7 1
G
+USB_VCCA
1 C405 @ 10P_0402_50V8J 2
1
D20 @ PSOT24C_SOT23
VCC DD+ GND
D
+3VALW
1 2 3 4
S
+5VALW
USBP4USBP4+ 3
21 21
2
1
C349 2
1
1
2
2
C355 1000P_0402_50V7K
0.1U_0402_16V4Z JP22
2
USBP3USBP3+ 3
21 21
D19 @ PSOT24C_SOT23
C358 @ 10P_0402_50V8J
1
1
2
2
For EMI
C361 5 @10P_0402_50V8J6 7 8
1
2
1 2 3 4
VCC DD+ GND GND1 GND2 GND3 GND4
2
SUYIN_020173MR004G552ZR
LED Function
+5VALW R86
33 CHARGE_LED1#
2
3
R84
1
CHARGE0 4 2 130_0402_5%
3
R83
1
CHARGE1 2 2 130_0402_5%
1 33
19-22SURSYGC/S530-A2/TR8_G/R
PWR_LED#
PWR_LED#
2
1 PWR_D 1
330_0402_5% 17-21SYGC/S530-E1/TR8_GRN
23
Q17
D11
HDACT_R 2
2 3
PWR_R D10 33 CHARGE_LED0#
+5VS R85
D12
HDD_ACT#
HDD_ACT# 2
1HDACT_D 1
2
17-21SYGC/S530-E1/TR8_GRN 330_0402_5%
Q16
1
PDTA114EK_SC59
1
PDTA114EK_SC59
3
3
SWDJ Board
T/P Board
1394/USB Board
For EMI +5VS JP5 1 2 3 4 5 6 7 8 9 10
+5VALW
C552 0.1U_0402_16V4Z 1 2 SWDJ_ON/OFF# KSI0 KSI3 KSI2 KSO16 KSI1 WL_BT_LED WL/BT_BTN#
+5VALW JP25 1 2 3 4 5 6 7 8 9 10 11 12 13 14
JP6
SWDJ_ON/OFF# 34 KSI0 33 KSI3 33 KSI2 33 KSO16 33
1 2 3 4 5 6
KSI1 33 WL_BT_LED 28 WL/BT_BTN# 33
PSDAT3 33 PSCLK3 33
ACES_85201-0605
ACES_85201-1005 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14
XTPA0XTPA0+ XTPB0XTPB0+ SYSON#
XTPA0XTPA0+ XTPB0XTPB0+
27 27 27 +3VALW 27
1 2 R361 10K_0402_5% OVCUR#0
OVCUR#0 21
USBP0+ USBP0-
USBP0+ USBP0-
21 21
USBP1+ USBP1-
USBP1+ USBP1-
21 21
4
ACES_87213-1400
Compal Electronics, Inc. Title
USB Port THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Size Document Number Custom LA-2592 Date:
Rev 0.2 Sheet
Tuesday, February 15, 2005 E
32
of
46
A
B
C
D
E
+3VALW
C291
C106
2 2 0.1U_0402_16V4Z
1000P_0402_50V7K
R206 For PM M/B(High) R214 For GM M/B(Low)
1
C345
C366 2
+3VS
R196 47K_0402_5%
+3VALW
21 EC_SCI# 21,24,27,28 CLKRUN#
75 BATTEMP/AD0/GPIO38 BATT OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A AD BID0/AD3/GPIO3B AD INtput or GPI
71 72 73 74
BATT_TEMP BATT_OVP M/B_ID
CP3
BATT_TEMP 38 BATT_OVP 37 ADP_I 37
KSO2 KSO4 KSO7 KSO8
76 78 79 80
DAC_BRIG 16 EN_FAN1 15 IREF 37 VOLUME_CTRL 31
INVT_PWM/GPIO0F/PWM1 BEEP#/GPIO10/PWM2 OUT BEEP/GPIO12/PWM3 ACOFF/GPIO18/PWM4 FAN SPEED1/GPIO14/FANFB1 FAN SPEED2/GPIO15/FANFB2
25 27 30 31 32 33
INVT_PWM 16 BEEP# 29 PWR_LED# 32 ACOFF 37 FAN1SPD 15 LVDSBIA 16
PSCLK1 PSDAT1 PSCLK2 PSDAT2 PSCLK3 PSDAT3
91 92 93 94 95 96
CAMERA_ONOFF2 G EC_IDERST# 23 ON/OFFBTN_LED# 17 CHARGE_LED1# 32 PSCLK3 32 PSDAT3 32
PWR
+5VALW
KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15
1
16
KSO16 32 KSO16 NV44_ENBKL 1 2 R134 VGA@ 100K_0402_5% SMB_EC_DA2 15,29 SMB_EC_DA2 SMB_EC_CK2 15,29 SMB_EC_CK2 SMB_EC_DA1 34,38 SMB_EC_DA1 SMB_EC_CK1 34,38 SMB_EC_CK1
NV44_ENBKL
GATEA20
1
R263 10K_0402_5%
1
R273 10K_0402_5%
2
2
+3VS
GATEA20
KBRST#
KBRST#
EC DEBUG port 3
JP7 1 2 3 4
SLP_S4# UTX
+3VALW
+5VALW
@ ACES_85205-0400
17
21 RSMRST# 16 BKOFF# 21 SLP_S3# 21 LID_SWOUT# 21 SLP_S5# 21 EC_SMI# 23,29 EC_IDERST
SLP_S3# LID_SWOUT# SLP_S5# EC_SMI#
16,34,35,40,41 SUSP# 21 PWRBTN_OUT# 19,24,28 ICH_PME#
+3VS
3 2
XCLKO XCLKI
4 @ 20M_0402_5% R286 IN 1 Y1 32.768KHZ_12.5P_1TJS125DJ2A073 C RY1 1 2 NC
OUT
ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7 KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7 KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15 KBA16 KBA17 KBA18 KBA19
125 126 128 130 131 132 133 134 111 112 113 114 115 116 117 118 119 120 121 122 123 124 110 109 108 107 106 98
SELIO2#/ GPIO43 SELIO#/ GPIO50 FRD#/RD# FWR#/WR# FSEL#/SELMEM#
84 97 135 136 144
+VCCP_PWRGD 7 EC_MUTE# 31 FRD# 34 FWR# 34 FSEL# 34
41 43 29 36 45 46
EC_ON 34 ACIN 36,39 EC_THRM# 21 ON/OFF 34 WL/BT_ON 17,28 ICH_PWRGD 21
Address BUS SM BUS
EC ON/ GPIO1B AC IN/ GPIO1C ECTHERM#/GPIO11 ONOFF/GPIO18 PCMRST#/GPIO1E WL OFF#/GPIO1F ALI/MH#/GPIO40 FSTCHG/GPIO41 VR ON/ GPIO42 GPIO57/GPIO57 GPIO58/GPIO58 GPIO59/GPIO59
81 82 83 137 142 143
ICH_PWRGD MSEN#
D
CAMERA_ONOFF# 32
Q44 CAMERA@ 2N7002_SOT23
S
@ 100P_1206_8P4C_50V8 CP6 KSI1 KSI7 KSI6 KSO9
@ 100P_1206_8P4C_50V8 CP5 1 8 2 7 3 6 4 5
2
@ 100P_1206_8P4C_50V8 CP2 KSO6 KSO3 KSO12 KSO13
1 2 3 4
8 7 6 5
@ 100P_1206_8P4C_50V8 CP1 1 8 2 7 3 6 4 5
KSO14 KSO11 KSO10 KSO15
SP010020100
ADB[0..7] 34 KBA[0..19] 34
8 7 6 5
KSI4 KSI5 KSO0 KSI2
ACES_85202-2405 ADB[0..7] KBA[0..19]
1 2 3 4
@ 100P_1206_8P4C_50V8
+5VALW
PSCLK3 2 1 10K_0402_5% R243 PSDAT3 2 1 10K_0402_5% R246
+3VALW 3
FSEL# R288 1 10K_0402_5% 2 FR D# R287 1 10K_0402_5% 2 EC_SMI#R231 1 10K_0402_5% 2
MSEN# 17 FSTCHG 37 VR_ON 42 SW DJ_ON/OFF 34 SWDJ_RST_HOLD 23 PROCHOT# 4
KB910L_LQFP144
SA009100100(RevA0)->SA009100110(RevA1)
NC
2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
140 138
PSCLK3 PSDAT3
ADB0/D0 ADB1/D1 ADB2/D2 ADB3/ D3 ADB4/D4 ADB5/D5 ADB6/D6 ADB7/D7 KBA0/A0 KBA1/A1 KBA2/A2 KBA3/A3 KBA4/A4 KBA5/A5 KBA6/A6 KBA7/A7 KBA8/A8 KBA9/A9 KBA10/A10 KBA11/A11 KBA12/A12 KBA13/A13 KBA14/A14 KBA15/A15 KBA16/A16 KBA17/A17 KBA18/A18 KBA19/A19
Data BUS
EC_RSMRST#/ GPIO02 BKOFF#/GPIO03 PM SLP S3#/GPIO04 EC LID OUT#/GPIO06 PM SLP S05#/ GPIO07 EC SMI#/GPIO08 EC SWI#/GPIO09 LID SW#/ GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C EC PME#/GPIO0D
EC_IDERST# ON/OFFBTN_LED#
CAMERA_ONOFF#
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# LPC_LDRQ0# PCIRST# R275 2 R270 1 SIRQ
+3VALW
10P_0402_50V8J C363 +EC_AVCC
Close to RTC pad
L12 0_0603_5%
4
ECAGND 2
4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
C RY2
2
10P_0402_50V8J C362
JP9
ICH_PME#
4 7 8 16 17 18 19 20 21 22 23
PS2 interface
PCM_SPK#/EMAIL_LED#/ GPIO16 SB_SPKR/PWR_SUSP_LED#/ GPIO17 PWRLED#/ GPIO19 NUMLED#/ GPIO1A BATT CHGI LED#/ E51CS# BATT LOW LED#/ E51MR0 CAPS LED#/ E51TMR1 ARROW LED#/ E51 INT0 SYSON/GPIO56/ E51 INT1
1
1
+5VS
EC SMD2/ GPIO47/SDA2 EC SMC2/GPIO46/SCL2 EC SMD1/GPIO44/SDA1 EC SMC1/GPIO44/SCL1
34 35 38 40 99 SCROLLLOCK#101 100 WL/BT_BTN# 102 104
LID_SW#
FOR LPC SIO DEBUG PORT
88 87 86 85
UTX SLP_S4#
21 SLP_S4# 23,29 CD_PLAY 17 NUMLOCK# 32 CHARGE_LED0# 17 SCROLLLOCK# 17 CAPLOCK# 32 WL/BT_BTN# 35,41 SYSON
R192 10K_0402_5%
key Matrix scan KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F EC URXD/KSO16/GPIO48 EC UTXD/KSO17/GPIO49
R455 CAMERA@ 10K_0402_5%
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1
1 2 3 4
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 89 90
139 129 103 13 28 39
2
SMB_EC_DA1 SMB_EC_CK1 SMB_EC_DA2 SMB_EC_CK2
2
2
R233 4.7K_0402_5% R236 4.7K_0402_5%
2
R229 R227 4.7K_0402_5% 4.7K_0402_5%
1
1
1
2
KSI0/GPIO30 KSI1/GPIO31 KSI2/GPI032 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPI035 KSI6/GPIO36 KSI7/GPIO37
AGND
KSI4 KSI5 KSI6 KSI7
63 64 65 66 67 68 69 70
77
KSI0 KSI1 KSI2 KSI3
KSI0 KSI1 KSI2 KSI3
GND GND GND GND GND GND
32 32 32 32
1
FAN/PWM
KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15
8 7 6 5
KSI3 KSO5 KSO1 KSI0
JP4
+5VS
1 2 3 4
@ 100P_1206_8P4C_50V8 CP4 1 8 2 7 3 6 4 5
INT_KBD CONN.
DAC_BRIG/DA0/GPIO3D EN DFAN1/DA1/GPIO3D IREF2/DA2 EN DFAN2/DA3/ GPIO3F DA output or GPO
2
19,24,25,27,28 PCIRST#
1 2 1 2 C328 R240 @ 15P_0402_50V8J @ 33_0402_5%
1
ECAGND 2 C295 0.01U_0402_16V7K
1
LPC_LAD[0..3]
20 LPC_LAD[0..3] 18 CLK_33M_LPCEC
GA20/ GPIO00/GA20 KBRST#/GPIO01/KBRST# SERIRQ LPC_FRAME# / LFRAME# LPC AD3/LAD3 LPC AD2/LAD2 Host LPC AD1/LAD1 INTERFACE LPC AD0/LAD0 CLK_PCI_EC/PCICLK PCIRST# EC RST#/ ECRST# EC SCI#/SCI#/GPIO0E PM_CLKRUN#/ CLKRUN#
1
3
GATEA20 1 KBRST# 2 SIRQ 3 LPC_LFRAME# 5 LPC_LAD3 6 LPC_LAD2 9 LPC_LAD1 10 LPC_LAD0 12 14 PCIRST# 15 ECRST# 42 EC_SCI# 24 CLKRUN# 44
EC_AVCC / AVCC
U20
21,25 SIRQ 20 LPC_LFRAME#
BATT_TEMP
11 26 37 105 127 141
JOPEN2 SHORT PADS
C304 2
@ 0.1U_0402_16V4Z
1 C290 0.1U_0402_16V4Z
2
2
20
1
2
R252 @ 10K_0402_5% 1 2
ECRST#
1
20
M/B_ID
R214 NONVGA@ 0_0402_5%
+EC_AVCC
VCC/ EC VCC VCC / EC VCC VCC / EC VCC VCC / EC VCC VCC VCC
2
1
R206
VGA@ 100K_0402_5%
1
2 2 1000P_0402_50V7K
1
+3VALW
0.1U_0402_16V4Z 1 C336
2
0.1U_0402_16V4Z 1 1
1
1
+3VALW
LPC_LDRQ0# 20
L13
1@ 10K_0402_5% 2 @ 22_0402_5%CLK_33M_LPCEC
1 C315
2
1
2 0_0603_5%
0.1U_0402_16V4Z
Compal Electronics, Inc. Title
KBD EC CTRL-KB910L THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
@ ACES_85201-2005 A
B
C
D
Size
Document Number
Rev 0.3
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 E
33
of
46
A
B
C
D
E
+3VALW R57 1
2 C109 @ 0.1U_0402_16V4Z INT_FLASH_EN#
R60 @ 10K_0402_5%
1
Power BTN
OE#
O
U11
@ 22_0402_5%
FSEL#
2
I
FSEL#
33 1
@ 74LVC1G125GW_SOT3535
R56 100K_0402_5%
3
R55 100K_0402_5%
4
2
G
1
1
1
1
5
1 2
R59 INT_FSEL#
2
C108 @ 0.1U_0402_16V4Z 2 1
P
+3VALW
@ 100K_0402_5%
1
2
2
D6 2
SW DJ_ON/OFF 33
1
R58
51ON#
3
1
2
SWDJ@ DAN202U_SC70
0_0402_5%
INT_FLASH_SEL
4
D4
O
74LVC1G125GW_SOT3535 2 C107 1000P_0402_50V7K
2
2
I
SUS_STAT#
SUS_STAT# 21
G
1
DTC124EK_SC59 1
SB_INT_FLASH_SEL# 21
5
36
U33
2
EC_ON
EC_ON
51ON#
RLZ20A_LL34
3
33
51ON# Q9
2
R53 4.7K_0402_5%
1
1
DAN202U_SC70
ON/OFF 33
P
2 +3VALW
ON/OFF
OE#
3 1
1
+3VALW C540 0.1U_0402_16V4Z 1 2 SB_INT_FLASH_SEL#
D5 ON/OFFBTN#
17 ON/OFFBTN#
3
SWDJ_ON/OFF#
32 SWDJ_ON/OFF#
+3VALW 1
+3VALW
R54 @ 100K_0402_5%
SUSP#
2
16,33,35,40,41
5
2 G
2
KBA[0..19]
ADB[0..7]
KBA[0..19] 33
1
1
3 @ 2N7002_SOT23
FW R#
512K FLASH ROM U14 KBA18 KBA16 KBA15 KBA12 KBA7 KBA6 KBA5 KBA4 KBA3 KBA2 KBA1 KBA0 ADB0 ADB1 ADB2 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
FWR# KBA17 KBA14 KBA13 KBA8 KBA9 KBA11 FR D# KBA10 INT_FSEL# ADB7 ADB6 ADB5 ADB4 ADB3
+3VALW 2
1
Alternative SA290080100 C120
1MB ROM SOCKET
0.1U_0402_16V4Z
+3VALW 1
+3VALW
1 R226 100K_0402_5%
2 8 7 6 5
33,38 SMB_EC_CK1 33,38 SMB_EC_DA1
VCC WP SCL SDA
33
FRD#
2
U19 A0 A1 A2 GND
+3VALW
U12
BIOS SOCKET-DC040043905
C324
33
1MB FLASH ROM
A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
SST39VF040-70-4C-NH_PLCC32
0.1U_0402_16V4Z
EC_FLASH# 21
S
2
I1
D
I0
O
U10 @ TC7SH32FU_SSOP5
ADB[0..7] 33
P 4
3
FWR#
G
2
Q8
1 2 3 4
KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7 KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15 KBA16 KBA17 KBA18 KBA19
21 20 19 18 17 16 15 14 8 7 36 6 5 4 3 2 1 40 13 37
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
INT_FSEL# FR D# FWR#
22 24 9
CE# OE# WE#
VCC0 VCC1
31 30
D0 D1 D2 D3 D4 D5 D6 D7
25 26 27 28 32 33 34 35
ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7
RP# NC READY/BUSY# NC0 NC1
10 11 12 29 38
RESET#1
GND0 GND1
23 39
JP8
1 2 R294 @100K_0402_5%
+3VALW
KBA16 KBA15 KBA14 KBA13 KBA12 KBA11 KBA9 KBA8 FWR# RESET#1 INT_FLASH_EN# INT_FLASH_SEL KBA18 KBA7 KBA6 KBA5 KBA4 KBA3 KBA2 KBA1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
KBA17 KBA19 KBA10 ADB7 ADB6 ADB5 ADB4
3
+3VALW ADB3 ADB2 ADB1 ADB0 FR D# FSEL# KBA0
SUYIN_80065AR-040G2T
@ SST39VF080-70_TSOP40
1
AT24C16AN-10SI-2.7_SO8
2
R228 100K_0402_5%
4
4
Compal Electronics, Inc. Title
BIOS & EXT. I/O PORT & PW BT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Size Document Number Custom LA-2592 Date:
Rev 0.2 Sheet
Tuesday, February 15, 2005 E
34
of
46
5
4
+3VALW
+3VS
3
2
1
+2.5V
+3VALW to +3VS Transfer
Q33 8 7 6 5
C352 22U_1206_10V4Z
D D D D
S S S G
1 2 3 4
R281 470_0402_5%
AO4422_SO8 C350 10U_0805_10V4Z
C351 22U_1206_10V4Z
D
C380 C382 22U_1206_10V4Z 0.1U_0402_16V4Z 1
D
D
RUNON
3
S
+5VS
+3VS
Q30 SYSON# 2 G 2N7002_SOT23
+2.5VS
+1.5VS
+1.25VS
+VCCP
+5VALW to +5VS Transfer +5VALW R76 470_0402_5%
+5VS
R75 470_0402_5%
R74 470_0402_5%
R72 470_0402_5%
R68 470_0402_5%
R62 470_0402_5%
2
2
Q11
S
SUSP 2 G 2N7002_SOT23
D
1
S
SUSP 2 G 2N7002_SOT23
Q10
S
SUSP 2 G 2N7002_SOT23
D
3
Q12
D
1
S
SUSP 2 G 2N7002_SOT23
3
Q13
D
1
SUSP 2 G 2N7002_SOT23
3
S
Q14
D Q15 2 SUSP G 2N7002_SOT23 S
1
C448 22U_1206_10V4Z
AO4422_SO8 R92 100K_0402_5%
C
1
RUNON D
3
SUSP
D
3
C450 0.1U_0402_16V4Z 1
1
1 2 3 4
S S S G
1
C
D D D D
3
1
C480 10U_0805_10V4Z
8 7 6 5
3
Q39 C481 10U_0805_10V4Z
+12VALW
S
R99 1M_0402_5% Q19 2N7002_SOT23
2 G
C136 0.01U_0402_16V7K
1
+5VALW
+2.5V to +2.5VS Transfer
33,41
Q4 8 7 6 5
B
D D D D
S S S G
1 2 3 4
SYSON#
SYSON#
1
+2.5VS
D
3
32 +2.5V
2
R280 47K_0402_5%
S
Q31 2N7002_SOT23
2 G
SYSON
B
C141 22U_1206_10V4Z
AO4422_SO8 C8 10U_0805_10V4Z
C15 0.1U_0402_16V4Z
RUNON +5VALW
1
C11 @0.1U_0402_16V4Z
2
R285 10K_0402_1%
16,33,34,40,41 SUSP#
LM358A_SO8
B
SN74LVC08APW_TSSOP14
13
A
S
Q32 2N7002_SOT23
B
13
U13D O
U17D
11
12
I
OE#
12 11
P
U16D O
D
2 G
O
11
G
13
-IN
A
P
14
7
7
6
OUT
G
A
12
+IN
7
5
SUSP#
+3VALW 14
+3VALW U6B
SUSP 1
SUSP
3
16,40
A
SN74LVC08APW_TSSOP14
SN74LVC125APWLE_TSSOP14
Compal Electronics, Inc. Title
POWER CONTROL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size Custom Date:
Document Number
Rev 0.1
LA-2592 Sheet
Tuesday, February 15, 2005 1
35
of
46
A
B
C
D
E
Detector
Vin Detector 18.234 17.841 17.597 17.210
1
VIN PL1 FBM-L18-453215-900LMA90T_1812 ADPIN 1
2 PR1 1M_0603_0.5% 1 2
VIN 1
VIN 1
VS
-
PR4 1K_0603_5% 2
1
PACIN
1
O
ACIN
33,39
2
2
PR3 10K_0805_5%
PACIN
37
1
+
2
PC5 0.01U_0603_50V7K
PU1A LM393M_SO8
1
3
4
PR7 10K_0603_5%
PZD1 2
RLZ4.3B_LL34 2
1
PC7 1000P_0603_16V7K
2
PR6 19.6K_0603_1% 2 1
1 2
2
8
PR5 22K_0603_1% 2
1 PC6 0.047U_0603_16V7K
1
PR2 82.5K_0603_1% 2
1
PC4 1000P_0402_50V7K 2 1
2
PC3 100P_0603_50V8J
PC2 1000P_0402_50V7K
PC1 100P_0603_50V8J 2 1
1
PC132 0.1U_0805_25V7K
SINGA_2DC-S756B200
2
1 2
3
PC133 680P_0402_50V7K 2 1
2
P
1 G G
G
ADPIN PCN1
1
17.449 16.813
PR8 10K_0603_5% 2 1
2
RTCVREF
3.3V
PR9 1
2
B+
1.5K_1206_5%
VIN
PR10 1
PD1 2
1
1.5K_1206_5%
2
1
1N4148_SOD80
PR11 PR12
PD3
1
VL
PR13 100K_0402_1% 2
2
PR14 2.2M_0402_5% 1
1
PD4 2
ACON
3
2
2
1
200_0603_5%
OUT
IN
4
2
1
2
PC14 1U_0805_50V4Z
BATT Detector H-->L 7.02 L---H 5.85
1 2
1
2
PR18 191K_0402_1%
1 D
PR21 2 G
1 1
PR22 34K_0402_1% 2 1
2 PACIN 47K_0402_5%
S
3
1
P G
2
2
VL
2
GND PC15 10U_0805_10V4Z
15.97
PQ3 DTC115EUA_SC70 PQ2 2N7002_SOT23 +5VALWP
2
PR165 66.5K_0402_1%
4
3
1
16.388
15.562
6
1
2 200_0603_5%
L->H
5
-
7.3 6.21
7.68 6.46
2
1
3.3V
G920AT24U_SOT89
1
CHGRTC
PU2
2
200_0603_5% PR24
Max 15.243
+
O
PC13 1000P_0603_16V7K
1 PR20
1
2
8
1
1 RTCVREF
Precharge detector Min Typ H->L 14.589 14.84
7
1
RB751V_SOD323
ACIN
2
22K_0603_5%
PR23
PD5 2
20,38,39 MAINPWRON
PC12 0.1U_0603_16V7K
1
51ON#
PC10 0.1U_0805_25V7K
2
PR17 34
PC9 0.22U_1206_25V7K
2
2
PR16 100K_0603_1%
PU1B LM393M_SO8
PR15 499K_0402_1%
PC8 0.01U_0603_50V7K
1
1
37
2
TP0610K_SOT23
4
1
1
1 3
3
B+
VS
VS 1N4148_SOD80 PQ1
1
RB751V_SOD323
2 1.5K_1206_5%
PC11 1000P_0402_50V7K
2
BATT+ 3
1
2
PD2 2
1
PR19 499K_0402_1%
2
47_1206_5%
Compal Electronics, Inc. Title
Detector THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Size Date:
Document Number
Rev 0.1 Sheet
Tuesday, February 15, 2005 E
36
of
46
A
B
-INC2
+INC2
24
2
OUTC2 GND
23
3
+INE2
CS
22
4
-INE2 VCC(o)
21
1
4
2
1
1 PQ9 AO4407_SO8
2
5
FB2
6
VREF
OUT
20
VH
19
4700P_0603_50V7K 1K_0603_1% PR39
1
PC26 1 2
1 2 1K_0603_1% 1500P_0603_50V7K
7
FB1
VCC
1
18 PR40
8
-INE1
RT
17
9
+INE1
-INE3
16
10
OUTC1
FB3
15
11 12
ACOFF
33
OUTD
CTL
14
+INC1
13
-INC1
2 PC29
2
0.1U_0805_25V7K
1 2 68K_0603_5% PL3 PR43 PC30 1 2 1 2 47K_0603_1% 1500P_0603_50V7K
1
PR41
2
1
2
FSTCHG
BATT+
0.02_2512_1% 8.2U_IHLP-2525CZ-01_4A_+-20%2525CZ
33
PD8 SKS30-04AT_TSMA
1
1
2
LXCHRG
0.1U_0603_50V4Z
2
PR45
PQ11 DTC115EUA_SC70
MB3887_SSOP24 PC34
PC33 10U_1206_25VAK 2 1
PC28 1 2
ACOFF#
0.1U_0805_25V7K
PC32 10U_1206_25VAK 2 1
1
PC22 2200P_0402_50V7K 2
PC23 1 2
PR38
2 1 10K_0603_1%
174K_0603_1%
1
PR32 10K_0603_5%
4
2
N18 CHGSS
47K_0603_5%
3
VREF
PC25 1 2
PR42
1 PR44
0_0603_5%
5 6 7 8
1 1
2
1
1 PR33 47K_0603_1%
36
IREF
2
PR31
1
2
PC31 10U_1206_25VAK 2 1
2 1SS355_SOD323
33
VIN
1
1
1
1
2 S
PD7 ACOFF#
PC19
2
2
PQ12 2N7002_SOT23
3
2 G
2
D
2
PR35 31.6K_0603_1%
2 1
3K_0603_5%
PR37 10K_0603_1%
1
2
PACIN
PR36 2
PC24 0.1U_0603_16V7K 2 1
PACIN
PC27 0.1U_0603_16V7K
3
1 3
PR34 150K_0603_1%
2N7002_SOT23
ADP_I
Throttling -1 level: ADP_I=1.4V Throttling +1 level: ADP_I=1.14V
PQ10 S
AO4407_SO8 8 7 6 5
1 2 3
3 2 1
1
PU3
1
0.1U_0603_25V7K
PC21 1
2
D
2
0.02_2512_1%
2
2 G
ACON
1
PR29
33
36
1
PQ6
Change P/N 12/24
PR26
2
2200P_0402_50V7K
1
47K
PQ8 DTC115EUA_SC70
PR30 47K_0402_5% 1 2
PL2 FBM-L18-453215-900LMA90T_1812
1
2
B++
B+ P3
PC18 0.1U_0805_25V7K
1
PR28
2
1K_0603_5% 1
47K
2
3
PQ7 DTA144EUA_SC70
PC20 0.1U_0603_25V7K 2 1
1 1
Iadp=0~3A
8 7 6 5
4
2
PD6 1SS355_SOD323
1 2 3
4
PR25 15K_0603_5%
1 2 3
PR27 200K_0603_5%
2
1
8 7 6 5
PQ5 AO4407_SO8
P2
PQ4 AO4407_SO8
D
PC16 10U_1206_25VAK 2 1
VIN
C
2
2
100K_0603_1%
IREF=1.096*Icharge IREF=0.44~3.3V
0.1U_0603_16V7K PR46
2
PR47
4.2V
1
2
150K_0603_0.1%
1
150K_0603_0.1%
CC=0.4~3A CV=12.6V(6 CELLS LI-ION)
3
PR48
2
1
3
150K_0603_0.1%
OVP voltage : LI
+3VALWP
VMB
3S2P : 13.5V--> BATT_OVP= 1.50V
CHGSS
1
1
(BAT_OVP=0.1111 *VMB)
D
S
2
@ 47K_0603_5%
1
PR50 340K_0603_1%
3
PR49
PQ13
2 G
1
2
VS
@2N7002_SOT23
P
5
-
6
1
4
1
PU5B LM393M_SO8
4
+
O 4
7
33 BATT_OVP
G
8
2
PR51 499K_0603_1%
PC36 0.01U_0603_50V7K
2
105K_0603_0.5%
2
PR52
Compal Electronics, Inc. Title
CHARGER Size Date: A
B
C
Document Number
Rev 0.1
Tuesday, February 15, 2005 D
Sheet
37
of
46
A
B
C
D
VMB PL4 FBM-L18-453215-900LMA90T_1812 1 2
PCN2
BATT+
PR57
1
+3VALWP
PR55 1K_0603_5%
PC37 1000P_0603_50V7K
PC38 0.01U_0603_50V7K VL VS 1
1
2
100_0603_5%
PC39 0.1U_0402_10V6K
2
1
2
2 47K_0603_5%
PH1 under CPU botten side : CPU thermal protection at 90 +-3 degree C Recovery at 50 +-3 degree C
CPU
PC40 0.1U_0603_50V4Z
2
PH1
1
PR56 100_0603_5%
1
2
PR54
2
1
@
1
1 1K_0603_5%
2
2 PR53
1
SUYIN_200275MR007G113ZL 1
1 2 3 4 5 6 7
1
9 8
BATT+ ID B/I TS SMD G SMC G GND
VL
2
10KB_0603_1%_TH11-3H103FT PR58
PR60 47K_0402_1%
VL
1
8 2
REV
2
2 SMB_EC_DA1 33,34
-
2 O
4
PR66 100K_0402_1%
2
+
2
1
1
LM393M_SO8
1
1
PR65 2.74K_0603_1%
3
PU5A
2
BATT_TEMP 33
2
1
PR64 100K_0402_1% PC42 0.22U_0805_16V7K
PD11 1SS355_SOD323
1
PR63 16.9K_0402_1% 1 2
PC41 1000P_0603_50V7K
SMB_EC_CK1 33,34
20,36,39
1
2
2
PR62 1K_0603_5%
P
1
PR61 0_0402_5%
MAINPWRON
+3VALWP
25.5K_0603_1%
G
2
1
1
2
PR59 47K_0402_1% 1 2
2
1
PQ15 DTC115EUA_SC70
3
2
3
3
4
4
Title
BATTERY CONN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Size
B
Document Number
Rev
LA-2592
0.1
Date: Tuesday, February 15, 2005
Sheet D
38
of
46
A
B
C
D
B+
+12VALWP
E
+3.3V/+5V
PR167
2 B
2
C
HMBT2222A_SOT23 PQ38 1 3
1
3K_0603_5%
1
PD26
change P/N(12/13)
RLZ13B_LL34 PL5 FBM-L18-453215-900LMA90T_1812
PC47 0.1U_0603_50V4Z 1 2
PD15 CHP202U_SC70
2
B+++
1 2 2
1
2
1
1 2 1 2 PR81 499K_0402_1% PR78 220K_0402_1%
1 4.7U_0805_6.3V6K PC126 2 1
PC59 1 330U_D_6.3VM
PR86 3.57K_0402_1%
2 PR87 0_0402_5%
+
2
change P/N(12/24)
1 2
PC62 0.1U_0603_16V7K
3
@
1
VL
change P/N(12/24)
+3VALWP
2 1
1 2
2
PC58 0.1U_0603_25V7K
PL7 TOKO_PLC-0745_8R2_3.8A
PR88 0_0402_5%
2VREF_1999
PR79 0_0402_5%
1
REF
2
7 2
PRO#
8
AO4912_SO8
10
12
8 7 6 5
D2 G2 D2 D1/S2/K G1 D1/S2/K S1/A D1/S2/K
28 26 24 27 22
2
ACIN
11
1
33,36
23 GND PC61 4.7U_0805_10V4Z 2 1 25 LDO3
1
5
2 1 2 PR80 499K_0402_1% PR77 220K_0402_1%
1 2 ILIM3
PC54 1U_0805_16V7K
17
LX5 PU6 DL5 MAX1999EEI_QSOP28ILIM5 OUT5 FB5 BST3 N.C. DH3 DL3 SHDN# LX3 ON5 OUT3 ON3 FB3 SKIP# PGOOD
VCC
15 19 21 9 1
1
PR85 0_0402_5%
1
2
2
PC52 10U_1206_25VAK
1 2 2
PC56 2 1 0.1U_0603_50V4Z
13
DH5
TON
BST5
6 4 3
PR84 10K_0402_5% 1 2
1 2 3 4
2VREF_1999
16
PC60 0.22U_0603_10V7K
@
PR83 47K_0402_5% 2 1
+
PR82
330U_D_6.3VM
+
2
10.2K_0402_1% 2
PC57 1
VS
1
PC131 1 330U_D_6.3VM
3
4.7U_0805_6.3V6K PC125 2 1
+5VALWP
PR76 4.7_0402_5%
14
V+
1
DL5
LD05
PL6 TOKO_PLC-0745_8R2_3.8A
18
PC55 4.7U_0805_10V4Z 2 1
2
VL
20
LX5 2
4.7U_1206_25V6K
PC53 2 1
2
AO4912_SO8
PQ17 PC50 0.1U_0603_16V7K
PC51 2200P_0402_50V7K
PR75 4.7_1206_5%
1
VS
2
PR72 4.7_0402_5%
2
DH5
1
8 7 6 5
PR74 47_0402_5%
D2 G2 D2 D1/S2/K G1 D1/S2/K S1/A D1/S2/K
1
1 2 3 4
PR73 0_0402_5% 5HG 1 2
1
PQ16
1
VL
PC49 10U_1206_25VAK 2 1
PC48 2200P_0402_50V7K 2 1
1
B+++
3
PC46 0.1U_0603_50V4Z 1 2
2
2
2
1
1
2
PR89 806K_0603_1% MAINPWRON 20,36,38
1
PJP1
1 @
2
+5VALW
PAD-OPEN 4x4m
PC63 0.47U_0603_16V7K
2
+5VALWP
PJP2
1
+3VALWP
2
@
4
+3VALW 4
PAD-OPEN 4x4m
Compal Electronics, Inc.
PJP9
2
+12VALWP
@
A
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Title OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS Size Document Number AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, Date: Tuesday, February 15, 2005 INC.
+12VALW
PAD-OPEN 2x2m
5V/3.3V
B
C
Rev
0.1 Sheet D
39
of
46
4
3
2
PR90 10_0402_5%
6
3
GND
8
LGATE
4
PC67 22U_1206_6.3V6M 2 1
PC66 22U_1206_6.3V6M 2 1
PD17 1N4148_SOD80 1 2 1
PC65 22U_1206_6.3V6M 2 1
AO4912_SO8 TOKO_0745-4R7_5A 1
PHASE
+1.5VSP/+1.25VSP
D
FB
S
PQ21 2N7002_SOT23
8 7 6 5
2
+1.5VSP
OCP 4.02A ~ 7.12A
PL8
APW7057KC-TR_SOP8
1 +
1
1
2
D2 G2 D2 D1/S2/K G1 D1/S2/K S1/A D1/S2/K
PC70 150U_D2_6.3VM
1
PQ20 2N7002_SOT23
D
2 G
2
S
2
3
,34,35,41 SUSP#
PR93 0_0402_5% 2 1
UGATE
OCSET
D
2 G 3
+3VALWP
PR92 100K_0402_5% 2 1
BOOT
PQ19 1 2 3 4
2 PAD-OPEN 3x3m
2
7
1
1
2
5 VCC
1
PC68 470P_0402_50V8JPU7
1
D
+5VALW
PJP3
1
PC69 0.1U_0402_16V7K
2 1 2
2 PR91 3.74K_0402_1%
PC64 1U_0603_10V6K
2
1
PC71 10U_1206_6.3V7K
5
1
PC72 1
PR94 9.31K_0402_1% 2
2
@ 0.1U_0402_16V7K
1
2 PC73 0.1U_0402_16V7K
1
PR95 10.5K_0402_1%
C
C
2
2.5VSP
PJP4 PAD-OPEN 3x3m
PJP5 2
+1.5VS
PU8 VIN
VCNTL
6
2
GND
NC
5
3
VREF
NC
7
4
VOUT
NC
8
TP
9
+5VALWP
2K_0402_1% 2
APL5331KAC-TR_SO8
+1.25VS
PQ22 2N7002_SOT23
PR98
+1.25VSP PC76 0.1U_0402_16V7K 1
S 2
PC77 @ 0.1U_0402_16V7K
2
B
D
2 G
1
PR97 0_0402_5% 1 2
2.05K_0402_1%
2
SUSP
1
16,35
2
PAD-OPEN 3x3m
1
2
1
1
3
+1.25VSP
PC78 10U_1206_6.3V7K
PJP6
1
1 PR96
2
PC74 10U_1206_6.3V7K
2
1
1
PAD-OPEN 3x3m
PC75 1U_0603_10V6K
1
1
+1.5VSP
B
A
A
COMPAL ELECTRONICS, INC Title
+12VP/+2.5VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size
Document Number
B
Rev 0.1
LA-2592
Date: Tuesday, February 15, 2005
Sheet 1
40
of
46
5
4
3
2
1
B+2
B+1
PC79 2200P_0402_50V7K
PJP10 2 @
1
+5VALWP
PJP11 1
2
PAD-OPEN 2x2m
@
B+
1
D
PAD-OPEN 2x2m
2
PR99 PC80 10U_1206_25VAK
0_0603_5%
PC99 2
1
1 2
2
@
PR169 2VREF
1 2
PC83 10U_1206_25VAK
1 2
1
4.7U_0805_6.3V6K PC128 2 1
1
15K_0402_1%
4.7U_0805_6.3V6K PC94 2 1
2 PR113 3.3K_0603_1% PR114 9.1K_0402_1%
C
2
2
PR110 SYSON
0.1U_0603_25V7K
33,35
PC96
1
2
PR108 15K_0603_5%
MAX8743EEI_QSOP28 3.3K_0603_1% 2 1 PR112 2 1
+
PC93 220U_D2_4VM
3 2 1 5 6 7 8 G S S S 4 3 2 1
1
13 3
1
B
16
1
0_0402_5%
PR170 1
3.74K_0402_1%
B
ILIM2 ILIM1
7 5
10K_0402_1%
REF
SKIP
10
6
GND
OVP
2
2
PC97
PR168 10K_0402_1%
@
D D D D
PC87 9
22
PGOOD TON
8
0.1U_0603_25V7K
2 PL11
PQ26 SI4810DY_SO8
1
ON1
15 14 12
2
11
23
+5VALWP
1
23.2K_0402_1%
PR111
1 0_0603_5% 1
2
2
OUT2 FB2 ON2
1
FB1
1
PR105 0_0603_5% 2
PR106
2
2
2
1
TOKO_0745-4R7_5A
PC88 0.1U_0805_50V7M 1
PR115 215K_0603_1%
CS1 OUT1
21 19 18 17 20 16
1
LX1 DL1
28 1
VDD BST2 DH2 LX2 DL2 CS2
2
27 24
PR109 SUSP#
2
2 DH1
UVP
BST1
26
2.5VSP
VCC
25
OCP 8.2A ~ 12.7A PR103 4.7_0603_5% 1 2
0.22U_0603_16V7K
PR107
16,33,34,35,40 SUSP#
5 6 7 8
1
1
1 PU9
2 PR104 0_0603_5%
S S S G
4 V+ 1U_0805_16V7K 2 1
1 2 3 8 7 6 5
1
4
VCC_MAX1845
1 2 3 4
1.27K_0402_1%
2 1
1
D D D D
PQ25 SI4810DY_SO8
PQ24
SI4800DY-T1_SO8~D PC86 0.1U_0805_50V7M 2 1
220U_D2_4VM
PL10
+ 2
2
PC84 4.7U_0805_10V4Z
2 PR102 4.7_0603_5%
2
PC90
1
1
PC85 0.1U_0805_50V7M
TOKO_0745-4R7_5A 1
4.7U_0805_6.3V6K PC91 2 1
C
4.7U_0805_6.3V6K PC127 2 1
+1.05VSP
4
2
3
8 7 6 5
20_0603_1% PQ23 SI4800DY-T1_SO8~D
OCP 6.11A ~ 9.42A
Change to Compal P/N(12/13)
PR101
2
Change to Compal P/N(12/13)
PR100 0_0603_5%
1U_0805_50V4Z PC81
1
PD18 DAP202U_SOT323
PC82 2200P_0402_50V7K
2
1
2
2
1
D
PR116 2 1
VCC_MAX1845 1 2.5VSP
PJP7 1
@ 0_0402_5% 2
PAD-OPEN 4x4m
+1.05VSP
2
@
PR117 0_0402_5%
+2.5V
PJP8 2 @
1
+VCCP
PAD-OPEN 2x2m
A
A
COMPAL ELECTRONICS, INC Title
+2.5VP / +1.05VP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size
Document Number
B
Rev 0.1
LA-2592
Date: Tuesday, February 15, 2005
Sheet 1
41
of
46
4
3
2
1
CPU CORE
2
14
BSTS
35
8
REF
DHS
33
9
ILIM
LXS
34
LXS DLS
OFS
DLS
32
3
SUS
CSP
40
18
SKIP
CSN
39
11
GND
GNDS
13
PD22 CHP202U_SC70 BSTM 2
PC104 68U_25V_M
1
1227 update 1
4
2
B
.56UH_MPC1040LR56_ 23A_20% 1
1
2 G 4 2
E
1
PL14
PQ34
RHU002N06_SOT323
2
PC114 PR146 0.022U_0402_16V7K @ 0_0402_5%
CPU_B+
PQ32 SI7392DP_SO8
1
1227 update
1 2 PR143 2K_0402_1%
+5VS
3
PR156 0_0402_5% 2
C
@
5 1 2
S
PC103 2200P_0402_50V7K
2
1 2 1
820_0402_5%
820_0402_5% 2
1
1 2 B
D
3
2
PSI#
C
1
PR157 10K_0402_1%
3 1 PQ37 HMBT2222A_SOT23
5
PR161 0_0402_5% 2 1
PR141
2 470P_0402_50V8J DHS
7
5
1 1 PC112
2
CCI
TON
1
CCV
2
2
0.47U_0603_16V7K
2K_0402_1% 2
12
1 FB
PR137 1
15
499_0402_1% 2 1
16
FB
PR135
OAIN-
TIME
PC110
499_0402_1% 2 1
SHDN#
1
SI7886DP_SO8 PQ28
PR134
6
OAIN
2
17
PR133
OAIN+
1
S1
10K_0402_1% 1
1
PR158 100K_0402_1%
PC102 0.01U_0402_25V7Z
2 1 PC100 10U_1206_25VAK 5
4
2
38 3 2 1
CMN
PD21 SKS30-04AT_TSMA
1 2
S0
PR127 2
0.001_2512_1%
SI7886DP_SO8 PQ35
2
2
PR155 +3VS
37
4
1
PR160 820_0402_5% 1
21 PM_DPRSLPVR B
CMP
2
@ 100K_0402_5%
S
MAX1532
2
PC120 0.01U_0402_25V7Z
PQ30 RHU002N06_SOT323 PR152 0_0402_5% 1 2
2
VROK
PC121 2 1
1
S
D
2 G
27P_0402_50V8J
1
2
0.22U_0603_16V7K
1
3 PR151 +3VS
D
2 G
2
1
PR148 0_0402_5% 1 2
1532REF
2
PR145 100K_0402_1%
18,21 H_STP_CPU#
1 PC113
PC115 100P_0402_50V8J
1
PR142 200K_0402_1%
PR147 10.7K_0402_1% 1 2
FB
2
270P_0402_50V7K
25
2 1 PC119 10U_1206_25VAK
PR144 71.5K_0402_1% 1 2
PC1111
2
31
D5
1
PD23 SKS30-04AT_TSMA
1
PGND
D4
19
.56UH_MPC1040LR56_ 23A_20%
PC117 2 1
@ 100K_0402_5%
30.1K_0402_1% TIME 1
DLM
1
2200P_0402_50V7K 2 1 PC118 10U_1206_25VAK
PR140 2
2
DLM
29
DHM
5
PR139 1
LXM
3_0402_5%
3 2 1
2
VR_ON
27
+CPU_CORE PL13
3 2 1
1532VCC 1 2 0_0402_5%
3
1 33
PR136
28
LXM
2
PR138 0_0402_5%
PC116 1 2
C
DHM
D3
PR149
18,21 VGATE
D2
21
4 PR124 0_0402_5% 2
3_0402_5%
VID5
22
1
VID4
5
BSTM
2
0.22U_0603_16V7K
5
2
PR130 0_0402_5%
PQ31 RHU002N06_SOT323
1
D1
26
PU10
5
1 PR121
23
20
+ 2
PQ27 SI7392DP_SO8
3 2 1
PC107 0.01U_0402_25V7Z
VID3
D0
10_0402_5%
VID2
5
VCC
24
PR150
5
10
1
VID1
0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 2
2
10K_0402_5% 1 5
2
PR125 1 2 @ 0_0402_5%
PR119 2 PR120 2 PR123 2 PR126 2 PR128 2 PR131 2 PR132 1
VID0
PR166
1532REF
1532VCC
5
PR122 @ 0_0402_5% 1532VCC 1 2
PC108 2 1
36
1 +3VS
BSTM 0.22U_0603_16V7K
30
V+
1
2
VDD
2.2U_0603_6.3V4Z
D
1
2
PC105 PC106 1U_0603_10V6K
2 1 PC101 10U_1206_25VAK
PL12 FBM-L18-453215-900LMA90T_1812 1 2
PR118 10_0402_5% 2 1
D
B+
CPU_B+
+5VS
PC109 1000P_0402_50V7K
5
1
2
PC122 0.47U_0603_16V7K
PR164 1
2 820_0402_5%
PC129
A
1
1000P_0402_50V7K OAIN 2
1
2
PC130
A
1000P_0402_50V7K
Compal Electronics, Inc. Title
CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size Document Number Custom
Rev 0.1
LA-2592
Date:
Sheet
Tuesday, February 15, 2005 1
42
of
46
5
4
3
2
Version change list (P.I.R. List) Item
Reason for change
Rev.
PG#
Change USB Power MOS form AATI4610AIGV-T1_SOT23-5 to RT9702ACB_SOT23-5 SA097020100
Cost down
Rev0.2
P31
2
Add new part U33 74LVC1G125GW_SOT3535 SA411250200 & C540 0.1U_0402_16V4Z SE070104Z00 & R366 10K_0402_5% SD028100200
HDD IOR# issue
Rev0.2
P31
3
Add new part C541 10U_0805_10V4Z SE053106Z00
HDD Power ripple
Rev0.2
P31
4
Del R412 0_0402_5% SD028000000
BITCLK 0 ohm passthought
Rev0.2
P31
5
Del R192(DPRSLP#)/R195(FERR#) 0_0402_5% SD028000000
Passthought Dothan B signal
Rev0.2
P31
6
BOM Del R136/R147 40.2_0402_1% SD034402A00
Intel recommand
Rev0.2
P31
7
Add new part C542/C543 10U_0805_6.3V6M SE093106K00
NB +VCCP Power ripple
Rev0.2
P31
8
Add new part R192 0_0402_5% SD028000000
Passthought FWR# to FWE#
Rev0.2
9
BOM del C377 100U_6.3V_M SF10001M100
USB Power 100UF * 2 -> 100UF *1
Rev0.2
P32
10
Del R412 0_0402_5% SD028000000
Del MODEM AC97 BITCLK 0 Ohm
Rev0.2
P30
11
BOM add C35 330U_D2E_2.5VM SGA19331D00
NB +2.5V Power ripple
Rev0.2
P10
12
BOM add C77 150U_D_6.3VM SG020151330
+2.5V Power ripple
Rev0.2
P14
13
BOM add C285 330U_D2E_2.5VM SGA19331D00
+CPU_CORE Power ripple
Rev0.2
P6
14
CRT LUMA/COMPS/CRMA & USBP6-/USBP6+ swap
layout swap avoid power noise cover
Rev0.2
P17
15
1394 PCI BUS swap PCI_AD[0..31]
1394 PCI BUS Layout update
Rev0.2
P27
16
Add new part R192 10K_0402_5% SD028100200
Lid SW# M/B pull high.
Rev0.2
P33
17
RTC BATT1 pin swap
RTC Battary pin define error
Rev0.2
P20
18
Del part R19 BOM part change R19 0_0603_5% to L21 BLM18PG600SN1_0603 SM010022000
CRT power filter noise NB power plan R19 -> L21
Rev0.2
P10
19
BOM change part 10 to 56: RP1, RP2, RP3,RP4,RP5,RP6,RP7,RP8,RP14,RP15,RP16,RP17,RP18,RP19,RP20,RP21 -> Rev0.1 BOM error 56_1206_8P4R_5% SD302560A00
Rev0.2
P13
20
BOM change part 10 to 56: R5,R6,R7,R8,R15,R16,R17,R18,23,R26,R28,R29,R30,R31,R36,R39 -> 56_0402_5% SD028560A00
Rev0.1 BOM error
Rev0.2
P13
21
Add new part C544,C545,C546,C548,C550 0.1U_0402_16V4Z SE070104Z00
NB Power plan filter
Rev0.2
P10
22
Add new part C549,C551,C547 0.22U_0603_16V4Z SE027224NT5
NB Power plan filter
Rev0.2
P10
23
Add new part L21,L22,L23,L24,L25 CHB1608U301_0603 SM010012500
NB Power plan filter
Rev0.2
P10
24
U20Pin93 – Del ON/OFFBTN_LED# JP15.Pin6 - chagne ON/OFFBTN_LED#
ON/OFFBTN_LED# need EC control, LED direct pull +3VS
Rev0.2
25
BOM D6 change 1N4148_SOT23 to DAN202U_SC70 SC2N202U0T4
SWDF ON/OFF# no function
Rev0.2
26
JOPEN1,JOPEN3,JOPEN4 follow JOPEN2 footprint
DFX review recommand
Rev0.2
27
JOPEN5,JOPEN6,JOPEN7 reserve MIC second rounting
For ME recommand
Rev0.2
P31
28
Rev0.2
P33
Pin73 - EC_IDERST Move to Pin19 Pin19 – ADP_I Move to Pin73
For EC Swap sagnal
1
Fixed Issue
Modify List
1
B.Ver#
Page 1 of 3
Phase
D
C
B
A
D
P31
C
5
B
to GND
P17,P33
A
P34
P20,P29
Compal Electronics, Inc. Title
PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
3
2
Size
Document Number
Rev 0.1
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 1
43
of
46
5
4
3
2
1
Version change list (P.I.R. List) Item
D
C
B
A
Page 2 of 3
Fixed Issue
Reason for change
Rev.
PG#
29
Del C443 0.47U_0603_16V7K SE026474KT6 Del BOM C445 1000P_0402_50V7K SE074102K00
Del +USB_VCCA CAF
Rev0.2
P32
Modify List
30
Add BOM R208 100K_0402_5% SD028100300
PM_DPRSLPVR stuff on resistor
Rev0.2
P21
31
Add new part R19 43K_0402_5% SD028430200
Option ENE1410 & TI1410 resistor
Rev0.2
P25
32
Add new part C443 150U_D_6.3VM SG020151330
NB power +2.5VS BOM non-stuff
Rev0.2
P10
33
Change BOM part U11 74AHCT1G125GW to 74LVC1G125GW_SOT3535 SA411250200
BIOS block schematic part change
Rev0.2
P34
34
Change BOM part L1 BLM18PG600SN1_0603 to 74BLM18PG330SN1_2P SM010019400
NB power +1.5VS ripple
Rev0.2
P10
35
Add net U20.pin93 EC_IDERST# for gating HD_IOR#
Gating HD_IOR#
Rev0.2
P33
36
Add BOM part R27 10K_0402_5% SD028100200 & C54 1000P_0402_50V7K SE074102K00
FAN schematic FAN1SPD stuff on pull high & CAF
Rev0.2
P15
37
Add new part R195,R412,R452 0_0402_5% SD028000000
Option SWDJ@ & NONSWDJ@
Rev0.2
P23
38
Del part R151,R152,R153,R154,R146,R158,R148,R138,R134
NB pin name CFG part change to test point.
Rev0.2
P07
39
Del part R131,R132
NB pin name SDVOCTRL change to test point.
Rev0.2
P09
40
ME change connector for LVDS/HDD/Keyboard/VGA B-B/Speaker/USB/RJ45/INT MIC
41
Del RJ45 LED function part R188, R224(10/100), R225(GLAN)
RJ45 connector no LED function
Rev0.2
P24
A2 MEMO
42
BOM AC10 0.01UF NPO SE069103K00 change to 0.01UF X7R SE000000H00
Short part
Rev0.2
P30
A2 MEMO
43
BOM AC11 SE168103M00 01U 250V M X7R 0805 change to SE093106K00 10U 6.3V M X5R 0805
BOM error
Rev0.2
P30
A2 MEMO
44
BOM U23 CB714 A revision change to B0 SA007140B10
Change revision and all BOM`s CB712 change to CB714.
Rev0.2
P25
A2 MEMO
45
BOM U20 KB910L A0 revision change to A1 revision SA009100110
Change revision
Rev0.2
P33
A2 MEMO
46
Add new part U34 74LVC1G125GW SA411250200
IDE_HDIOR# gating.
Rev0.2
P23
A2 MEMO
47
Add new part R131,R132 200 ohm 0402 SD028200000
For PCI-1410 BOM
Rev0.2
P27
A2 MEMO
48
Del part U11,R57,R59,R60,C108,C109 Add part R58 0 0402 +-5% SD028000000
FSEL# pass-through INT_FSEL#
Rev0.2
P34
A2 MEMO
49
Del part R206,C304
Signal M/B_ID
Rev0.2
P33
A2 MEMO
50
SMT JP29 un-marked
Rev0.2
P31
A2 MEMO
51
Del part C3, Add part C77
DDR +2.5V Cap change
Rev0.2
P14
A2 MEMO
52
BOM AR7,AR8 SD010200500 20M Ohm +-1% change to SD015200500 20M Ohm +-5%
Short part
Rev0.2
P21
A2 MEMO
53
BOM AC5,AC6,AC12,AC13 SE072104K00 0.1U 25V +-10% Y5V change to SE070104Z00 0.1U 16V +-10% Y5V
Short part
Rev0.2
P30
A2 MEMO
54
Del part R237
Del SB`s AC_IN
Rev0.3
P30
B MEMO
55
Change part DDR Hynix A die SA216220000 -> B die SA000023200
Chagne Hynix DDR version
Rev0.3
P12
B MEMO
56
NB's signal COMP/B & Y/G swap
Schematic pindefine error.
Rev0.3
P09
B.Ver#
Phase
D
C
Rev0.2
B
A
Compal Electronics, Inc. Title
PIR-2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size
Document Number
Rev 0.1
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 1
44
of
46
5
4
3
2
1
Version change list (P.I.R. List) Item
D
Fixed Issue
Reason for change
Rev.
PG#
57
Change BOM part Q5,Q6 2N7002 to BSS138
LVDS EDID Vih, Vil no match spec
Rev0.3
P16
58
Net GMCH_ENBKL connect to EC U20.p90 Add new part R134 100K pull down. Del part R11 0 ohm.
PM panel white back light issue.
Rev0.3
P21
59
C
Modify List
B.Ver#
Phase
D
Add new part C552,C553,C554,C555,C558,C559,D16,D17,D18,D19,D20.
EMI issue.
Rev0.3
60
Add new part R453,Q43.
For SWDJ geting RIQ.
Rev0.3
P23
61
Pop part R434.
For SWDJ A-A issue.
Rev0.3
P29
62
Change BOM part AC11 10U_0805 to 1U_1206
ME issue.
Rev0.3
P30
63
Add part C557,C558.
Boost audio "BO" sound issue.
Rev0.3
P31
64
Change BOM part R439,R80 0_0402 to 470_0402.
Ear phone sound too big issue.
Rev0.3
P31
65
Change BOM part JP28 footprint no match spec.
layout spec issue.
Rev0.3
P31
66
U6, U13, U16, U17 nc pin connect to GND.
Rev0.3
P35
67
Add jumper JOPEN5
EMI issue.
Rev0.3
P31
68
Add part C560 SE053475Z05 4.7U 10V Z Y5V 0805
Change Card Reader power MOS for MS card conn issue
Rev0.3
P26
69
Del BOM part Q34 SB923010010 SI2301BDS
Change Card Reader power MOS for MS card conn issue
Rev0.3
P26
70
Add part U34 SA005280100 G528
Change Card Reader power MOS for MS card conn issue
Rev0.3
P26
Rev0.3
P26
71
B
Page 3 of 3
P17,P31,P32
C
Change BOM part C374 SE076103K00 .01U 16V K X7R 0402 to SE070104Z00 .1U 16V Z Y5V 0402
Change Card Reader power MOS for MS card conn issue
72
Add part R454, C357. net EC_MUTE# pull high chanGe to +5V_AMP
For audio CD-L/R noise option +VDDA & +5VAMP.
Rev0.3
P31
73
Change BOM part R361 20K Ohm to 10K Ohm
For camera power switch.
Rev0.3
P32
C TEST BOM MEMO.
74
Add part R455, Q45, Q44, JOPEN7. Add net CAMERA_ONOFF&+5VS_CAM
For camera power switch.
Rev0.3
P33,32
C TEST BOM MEMO.
75
Change BOM part U26 to G528 for USB power MOS. For camera power switch. Change Net U26.4 to SYSON# & OVCUR#3 pull high +3VALW
76
Change BOM part U32 Change SA021210000 S IC APA2121RI_TR TSSOP-24 AUDIO AMP to SA002320300 S IC TPA0232PWP TSSOP-24 AUDIO AMP
B
For APA AMP audio power up "bo" sound
Rev0.3
P32
C TEST BOM MEMO.
Rev0.3
P31
C TEST BOM MEMO.
77 78 79 80 81 A
82
A
83 84
Compal Electronics, Inc. Title
PIR-3 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size
Document Number
Rev 0.1
LA-2592 Date:
Sheet
Tuesday, February 15, 2005 1
45
of
46
5
4
3
Version change list (P.I.R. List) Item D
Reason for change Update
2
Power section PG#
1.05V, 2.5V, 1.5V, 3.3V and 5V CHOKE for cost down
1
Page 1 of 2
Modify List
Date
B.Ver#
PL7, PL6, Pl10,PL11,PL8 update to TOKIN 4.5mm(High) from
38
Nov/12
1
VISHAY(3mm High)
2
Add Capacity 4.7UF 2 pcs
for reduce ribble voltage
3
Update BST Resistor to 4.7 ohm 2 pcs for reduce switching node noise
38
Add 4.7U in pC?
Nov/12
A.Ver#
38
PR72, PR76 update to 4.7 ohm from 0 ohm
Nov/12
A.Ver#
Update PD26 to 12V Zener from 16V Zener
Nov/12
A.Ver#
Nov/12
A.Ver#
4
Update 12VALWP 16V Zener to 12V Zener
38
5
Add CPU Thermal protect circuit
37
6
Delete Battery Thermal Protect circuit
37
7
Update Output Voltage to 1.26V from 1.25V
39
8
Reduce Ripple Voltage for 1.05V and 2.5V
40
Add 4.7U Capacity in pC128, PC127
Nov/12
A.Ver#
9
Update Out put Voltage to 1.054V from 1.05V
40
Update PR111 to 23.2K from 25.5K
Nov/12
A.Ver#
Reduce switching node noise
40
Update PR102,PR103 to 4.7 ohm from 0 ohm
Nov/12
A.Ver#
11
Reduce noise for SUSP#
40
Update PR1092,PR103 to 4. to 27 ohm from 0 ohm
Nov/12
A.Ver#
12
Reduce CPU noise for Vgate
41
Update PR166 to 10K from 100K
Nov/12
A.Ver#
Add PR61,PR65,PC42,PR63,PR64,PR66,PC41,PR59,PU5,PC40,PR60 PD11,PQ15 Delete PH2,PC43,PR68, PC45,PR70,PR71,PR67,PR69,PR14
D
A.Ver#
A.Ver#
Nov/12
C
C
10
A.Ver#
Update PR96 to 2K from 1K
Nov/12
Update PR98 to 2.05K from 1K
B
13
Reduce CPU noise
41
Update PL12 to 13A from 8A
Nov/12
A.Ver#
14
Reduce CPU switching node noise
41
Update PR121, PR149 to 3 ohm from 0 ohm
Nov/12
A.Ver#
15
Reduce CPU noise
41
Add 68UF Capacity in PC 129, PC104
Nov/12
A.Ver#
16
Adjust load line
41
Update PR137 , PR143 to 2K from 3K
Nov/12
A.Ver#
Delete PD24, PD25, PD19, PD20
Nov/12
for input side
Delete shocket Diode for Maxium 8743 and Maxium 1999 solution
40
38
B
A.Ver#
A
A
Compal Electronics, Inc. Title
PWR PIR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size Document Number CustomLA-2592 Date:
Tuesday, February 15, 2005
Rev 0.3 Sheet 1
46
of
46
