A
B
C
D
E
COMPAL CONFIDENTIAL 1
MODEL NAME : BDW00 COMPAL P/N : DA8DW00L110/DA8DW00L410 PCB NO : LA-1452 Revision : 1C DATE :
1
2
2
Abacus/TangII Schematics Document uFCBGA/uFCPGA Northwood 2003-02-24 3
3
REV: 1C
4
4
Dell-Compal Confidential Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 ¬P 期五, 四月 25, 2003
Sheet E
1
of
47
A
B
C
D
E
Block Diagram
Compal confidential Model Name : ABACUS/TangII File Name : LA-1452
CPU Bypass & CPUVID page 7,
Fan Control
1
page 7
+1.2VP
DT & Mobile Northwood uFCBGA/uFCPGA CPU
+CPU_CORE
8
Thermal Sensor +3VS
page 5,6
HA#( 3..31)
Clock Generator
ADM1032
1
ICS950810 +3VS
page 6
page 15
HD#(0..63)
System Bus 400/533 MHz
DT/BD-PE/ICH4/EXT VGA DT/BD-GL/ICH4/INT VGA
INTEL BROOKDALE-GL/PE 760 BGA
CRT Connector
page 17 INT. CRT
(PIRQE#,G_GNT#,G_REQ#) FOR EXT.
+1.5VS
EXT. CRT
+2.5V
AGP4X(1.5V) AGP GRAPHIC/CHRONTEL
AGP Conn
LVDS Connector
TV OUT
DDR-DIMM X2 BANK 0, 1, 2, 3
+2.5V 200/266MHz
+2.5V +1.25VS
page 12,13,14
+1.25VS +CPU_CORE
page 9,10,11
page 16
2
Memory BUS(DDR)
page 17
2
HUB LINK +1.5VS 66MHz
IDSEL:AD18 (PIRQC#D#,GNT#1,REQ#1)
Minipci CONN WIRELESS
+3VALW +3V +3VS
page 26
IDSEL:AD17 (PIRQB#,GNT#0,REQ#0)
page 22
+1.5VALW +CPU_CORE
24.576MHz
+3V
page 23,24,25
Card Bus SLOT page 24
AC-LINK
page 18,19,20
MDC +3VALW +3V page 29
LPC BUS +3VS 33MHz
1394
IDE CD-ROM
IDE HDD
CONN
+5VALW page 21
page 23
NS EC87591L Embedded Controller
845PE / PCI4510 845GL / PCI1510
+3VS +3VALW
+5VS page 21
SIDE IRQ15
Cable
AC97 Codec STAC9750 page 27
page 30
+5VALW page 28
Touch Pad
Int.KBD
LED Status LID Switch +5VS +5VALW +3VALW 4
page 34,35,36,37,38,39,40
DC/DC Interface Suspend
Power On/Off Reset & RTC
page 33
page 32
page 29
3
RJ11
+5VDDA
PIDE IRQ14
AMP & INT. Speaker
Power Circuit DC/DC
page 32
ATA100
VCC5REF VCC5REFSUS
+3VALW +5VALW
PCI4510/PCI1510
page 22
RJ45
3
+1.5VS
2 USB Ports
48MHz
INTEL ICH4 421 BGA
+3VALW
IDSEL:AD20 (PIRQA#,GNT#2,REQ#2)
CardBus & 1394
LAN BCM-4401L +3VS +3VALW
+3VS
PCI BUS
+3VS 33MHz
BIOS
+3VALW
HeadPhone & MIC Jack +5VDDA page 28
page 31
page 31 4
EC I/O Buffer +5VALW
EC DEBUG
page 31
+3VALW
page 30
Dell-Compal Confidential Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
2
of
47
5
4
3
Schematics Rev
PCB Rev
0.1
0.1
0.2
0.2
CHIPS Rev
+3VS
Signal
845PE Rev B0 845GL Rev B1 ICH4 Rev B0
D
PT-Build
1
Power Managment table
Revision List
SST-Build
2
State
+3VALW
+3V
+5VALW
+5V
+12VALW
+2.5V
+5VS +1.5VS +1.2VP D
+CPU_CORE +1.25VS
ST-Build
S0
ON
ON
ON
S1
ON
ON
ON
S3
ON
ON
OFF
S5 S4/AC
ON
OFF
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
QT-Build
Ceramic Capacitor Spec Guide: C
C
Temperature Characteristics: Symbol
0
1
2
3
4
CODE
Z5U
Z5V
Z5P
Y5U
Y5V
8
9
NP0
C0G
I
H UJ
A
B
C
BJ
CH
C
D
5 Y5P
6
7
X5R
X7R
D
E
F
G
CJ
CK
SH
SJ
J
UK
SL
Tolerance: Symbol B
CODE
K +-10%
A
B
+-0.05PF +-0.1PF +-0.25PF +-0.5PF
N
M +-20%
+-30%
P
F
G
+-1PF
+-2%
V
X
Q
H +-3%
J B
+-5%
Z
+100,-0% +30,-10% +20,-10% +40,-20% +80,-20%
SMBUS Control Table SOURCE
SMB_EC_CK1 SMB_EC_DA1
NS 87591
SMB_EC_CK2 SMB_EC_DA2
NS 87591
SMB_CLK SMB_DATA
ICH4
INVERTER
BATT
SERIAL EEPROM
THERMAL THERMAL SENSOR SENSOR SODIMM (CPU) (U57) (U25/U23)
NOTE1: CLK CHIP
MINI PCI
@XX :
Depop component
1@XX : Pop for INT, Depop for EXT (1010)
2@XX : Pop for EXT, Depop for INT
A
A
Dell-Compal Confidential Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: 5
4
3
2
Compal Electronics, Inc. SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 ¬P 期五, 四月 25, 2003
Sheet 1
3
of
47
5
4
3
2
1
PQ26
+1.5VALW
SUSP#
SHDN#
D
+5VS
SUSP#
+5VALW
+1.5VS page 35
page 35
D
page 31
SIDEPWR
+5VSHDD
page 21
SUSP#
MAX1632
+5VDDA
page 25
page 36
SYSON
+3VALW
+3V page 31
C
C
VR_ON#
page 34
SUSP#
AC
+3VS
page 31
B+
CM2843
+12VALW
Battery
+1.2V
page 38
VR_ON#
page 34
+5VS Mobile
+3VS
B
B
ISL6215 DT
+CPU_CORE
+1.5VS
VGA Conn. 180 pin
+2.5V +3V
page 38
ISL6219
+5VALW (Either one by CPU)
+12VALW B+
SUSP# A
SYSON
page 16
+1.25VS ISL6225
A
+2.5V
page 36
Dell-Compal Confidential Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5
4
3
2
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet 1
4
of
47
A
B
C
D
E
F
G
H
I
J
1
1
3
<9> H_REQ#[0..4]
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
J1 K5 J4 J3 H3 G1
H _REQ#[0..4]
H_ADS#
5 +CPU_CORE
<9> <9> <9> <9>
K2 K4 L6 K1 L3 M6 L2 M3 M4 N1 M1 N2 N4 N5 T1 R2 P3 P4 R3 T2 U1 P6 U3 T4 V2 R6 W1 T5 U4 V3 W2 Y1 AB1
H_BREQ0# H_BPRI# H_BNR# H_LOCK#
<15> CLK_CPU_BCLK <15> CLK_CPU_BCLK#
For Mobile R284 1
@4.7K_0402_5% 2
2 R301
1 200_0402_5%
CLK_CPU_BCLK CLK_CPU_BCLK#
AC1 V5 AA3 AC3 H6 D2 G2 G4 AF22 AF23
A#3 A#4 A#5 A#6 A#7 A#8 A#9 A#10 A#11 A#12 A#13 A#14 A#15 A#16 A#17 A#18 A#19 A#20 A#21 A#22 A#23 A#24 A#25 A#26 A#27 A#28 A#29 A#30 A#31 A#32 A#33 A#34 A#35 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 ADS# AP#0 AP#1 BINIT# IERR# BR0# BPRI# BNR# LOCK#
CPU CORE
DT/Mobile NorthWood CONTROL SIGNAL
<9>
HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31
HOST ADDRESS
4
U19A
HOST DATA
H A#[3..31]
BCLK0 BCLK1
6
GND F3 E3 E2
H_HIT# H_HITM# H_DEFER#
CPU CORE
HIT# HITM# DEFER#
H1 H4 H23 H26 A11 A13 A15 A17 A19 A21 A24 A26 A3 A9 AA1 AA11 AA13 AA15 AA17 AA19 AA23 AA26 AA4 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB21 AB24 AB3 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC2 AC22 AC25 AC5 AC7 AC9 AD1 AD10 AD12 AD14 AD16 AD18 AD21 AD23 AD4 AD8
VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56
<9> <9> <9>
2 HD#[0..63]
D#0 D#1 D#2 D#3 D#4 D#5 D#6 D#7 D#8 D#9 D#10 D#11 D#12 D#13 D#14 D#15 D#16 D#17 D#18 D#19 D#20 D#21 D#22 D#23 D#24 D#25 D#26 D#27 D#28 D#29 D#30 D#31 D#32 D#33 D#34 D#35 D#36 D#37 D#38 D#39 D#40 D#41 D#42 D#43 D#44 D#45 D#46 D#47 D#48 D#49 D#50 D#51 D#52 D#53 D#54 D#55 D#56 D#57 D#58 D#59 D#60 D#61 D#62 D#63
VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_80 VCC_79 VCC_78 VCC_77 VCC_76 VCC_75 VCC_74
HA#[3..31]
F13 F15 F17 F19 F9 F11 E8 E20 E18 E16 E14 E12
<9>
VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73
2
A10 A12 A14 A16 A18 A20 A8 AA10 AA12 AA14 AA16 AA18 AA8 AB11 AB13 AB15 AB17 AB19 AB7 AB9 AC10 AC12 AC14 AC16 AC18 AC8 AD11 AD13 AD15 AD17 AD19 AD7 AD9 AE10 AE12 AE14 AE16 AE18 AE20 AE6 AE8 AF11 AF13 AF15 AF17 AF19 AF2 AF21 AF5 AF7 AF9 B11 B13 B15 B17 B19 B7 B9 C10 C12 C14 C16 C18 C20 C8 D11 D13 D15 D17 D19 D7 D9 E10
+CPU_CORE
B21 B22 A23 A25 C21 D22 B24 C23 C24 B25 G22 H21 C26 D23 J21 D25 H22 E24 G23 F23 F24 E25 F26 D26 L21 G26 H24 M21 L22 J24 K23 H25 M23 N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24 Y21 AA25 AA22 AA24
HD#[0..63] <9>
HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
3
4
5
6
NorthWood
7
7 +CPU_CORE
Dell-Compal Confidential 8
Title
Compal Electronics, Inc.
8
SCHEMATIC, M/B LA-1452
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 401230 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom 星期五, 四月 25, 2003 Date:
A
B
C
D
E
F
G
H
I
R ev 1B Sheet
5
of
J
47
C
D 2 R267
E
F
G
H
I
J
H_SKTOCC#
1 @33_0402_5%
1
+CPU_CORE
2 R288
1 300_0402_5%
H_PWRGD
<9> <9> <15>
H_THERMDA H_THERMDC
+CPU_CORE
Place resistor <100mils from CPU pin
<8> <8>
ITP_PRDY# ITP_PREQ#
R207 0_0603_5%
<8> <8> <8> <8> <8>
ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST#
2 L24 1 L25 1
LQG21F4R7N00_0805 H_VCCA 2 LQG21F4R7N00_0805 1 H_VCCIOPLL 2 TP2 1 1 1 Murata LQG21F4R7N00 C321 C305 C320 1U_0603_10V4Z 22U_1206_10V4Z 2 2 2 H_VSSA 22U_1206_10V4Z RP61 CLK_CPU_ITTP 1 4 <15> CLK_CPU_ITP CLK_CPU_ITTP# 2 3 <15> CLK_CPU_ITP#
5 RP62 1 2
CLK_ITP# CLK_ITP
51.1_0603_1%
1 51_0402_5% 1 51_0402_5%
ITP_PREQ# ITP_PRDY#
R262 2 R272 2
1 51_0402_5% 1 51_0402_5%
ITP_BPM0 ITP_BPM1
R268 2 R296 2
1 51_0402_5% 1 51_0402_5%
ITP_BPM2 ITP_BPM3
1 R313 1 R305 1 R314
2 @1.5K_0402_5% 2 @1.5K_0402_5% 2 680_0402_5%
ITP_TDI
NC7 NC8
DBI#0 DBI#1 DBI#2 DBI#3 DBR# PROCHOT# MCERR# SLP#
ITP_CLK0 ITP_CLK1
GND
R300 51.1_0603_1%
NC3 NC4
56_0402_5%
R293 1 R276 1 R294 1
2 56_0402_5% 2 56_0402_5% 2 56_0402_5%
H _GHI# H_DSTBN#[0..3]
H_DSTBN#[0..3] <9>
3
H_DSTBP#[0..3]
H_DSTBP#[0..3] <9>
H_ADSTB#0 <9> H_ADSTB#1 <9> H_DBI#0 H_DBI#1 H_DBI#2 H_DBI#3
E21 G25 P26 V21
H_DBI#[0..3] <9>
2 1 @0_0402_5%
SYSRST# <19> H_ITP_DBR# <8>
C3 V6 AB26
H_PROCHOT# 1 R311 H_SLP#
AD22 A4
H_VSSA
2 62_0402_5%
1
5
+3VS
<8,40> <8,40> <8,40> <8,40> <8,40>
+CPU_CORE C317 0.1U_0402_16V4Z
R303 1K_0402_5%
2
49.9_0603_1%
<34,36> SHDN_1632#
VDD1
D-
ALERT#
SMB_EC_CK2
8
SCLK
SMB_EC_DA2
7
SDATA
1
1
R261
R_B
6
THERM#
4
GND
5
1
3
100_0603_1%
2
C319 1U_0603_10V4Z
1
2
3 47K_0402_5%
Q62 2N7002_SOT23
1
D+
2 Q64 MMBT3904_SOT23
C318 220P_0603_50V8J
8
Title
CPU Temperature Sensor
2 1
2
H_THERMTRIP#
Q59 MMBT3904_SOT23
Compal Electronics, Inc.
8
SCHEMATIC, M/B LA-1452
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 401230 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom 星期五, 四月 25, 2003 Date:
C
7
R320 470_0402_5%
Dell-Compal Confidential
ADM1032ARM_RM8
B
H_PROCHOT# <37>
R316
Trace width>=7mil
2
3
H_PROCHOT#
1. Place R_A and R_B near CPU (Within 1.5"). 2. Place decoupling cap 220PF near CPU.(Within 50 0mils)
2
2
2 H_THERMDC
2
2 Q26 MMBT3904_SOT23
<10,16,18,22,23,25,26,30,33> PCIRST#
Layout note :
+H_GTLREF1
U57 2
R_A
VL
2
1 R337 @10K_0402_5%
2
1
1
1
C174 0.1U_0402_16V4Z
8.2K_0402_5%
1
C470 2200P_0603_50V7K
2
R265
6
1
+CPU_CORE
R307 470_0402_5%
<19,31> PROCHOT#
1
+5VS
R333
<18>
AD2 AD3
GTL Reference Voltage
R334
+CPU_CORE
H_SLP#
ITP_TMS
H_THERMDA
4
R266
H_DBR#
AE25
1
1
A
56_0402_5%
NorthWood
CPU_VID4 CPU_VID3 CPU_VID2 CPU_VID1 CPU_VID0
ITP_TRST#
Width 10mil , Spacing 10mil
2
TP1
8.2K_0402_5%
<8,30> SMB_EC_DA2
2
+1.2VP
+5VS
<8,30> SMB_EC_CK2
VSSA VSSSENSE
COMP0 COMP1
If used ITP port must depop
7
L5 R5
ITPCLKOUT0 ITPCLKOUT1 TESTTHI8_10
3
6
R278 2 R291 2
1
0_4P2R_0402_5%
+CPU_CORE
ADSTB#0 ADSTB#1
1
H_D BI#[0..3]
AF25 AF3
R302
4 3
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
1
<8> <8>
F21 J23 P23 W23
TCK TDI TDO TMS TRST# VCCA VCCSENSE VCCIOPLL
L24 P1
DSTBP#0 DSTBP#1 DSTBP#2 DSTBP#3
NorthWood
BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5
AD20 A5 AE23
AC26 AD26
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
THERMTRIP#
2
2
@0_4P2R_0402_5%
D4 C1 D5 F7 E6
E22 K22 R22 W22
2
R275
3
For Mobile
ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST#
DSTBN#0 DSTBN#1 DSTBN#2 DSTBN#3
1 R285
TESTTHI2_7
2 G
2
@0_0603_5%
A2
ITP_BPM0 AC6 ITP_BPM1 AB5 ITP_BPM2 AC4 ITP_BPM3 Y6 ITP_PRDY# AA5 ITP_PREQ# AB4
1
1 R206
4
<19> H_THERMTRIP# <8> ITP_BPM0 <8> ITP_BPM1
+CPU_CORE
+1.2VP
H_THERMTRIP# 2 62_0402_5%
1 R315
DT/Mobile
THERMDA THERMDC
S
1 51.1_0603_1%
DBSY# DRDY# BSEL0 BSEL1
D
2 R279
B3 C4
H_RESET#
1
3
H5 H2 AD6 AD5
H_DBSY# H_DRDY# H_BSEL0
TESTTHI0_1
2
H_DPSLPR#
AD24 AA2 AC21 AC20 AC24 AC23 AA20 AB22 U6 W4 Y3 A6
1
1 200_0402_5%
TESTHI0 TESTHI1 TESTHI2 TESTHI3 TESTHI4 TESTHI5 ITPCLKOUT0 ITPCLKOUT1 TESTHI8 TESTHI9 TESTHI10 GHI#
+CPU_CORE
1
2 R271
1
+H_GTLREF1
AA21 AA6 F20 F6 A22 A7
VCCVID
<18> H_INTR <18> H_NMI <18> H_INIT# <8,9> H_RESET#
J26 K25 K26 L25
GTLREF0 GTLREF1 GTLREF2 GTLREF3 NC1 NC2
AF4
@0_0402_5% 2 1
NC5 NC6
H_DPSLP#
A20M# FERR# IGNNE# SMI# PWRGOOD STPCLK# DPSLP# LINT0 LINT1 INIT# RESET#
AE21 AF24
R269 <18>
H_A20M# C6 H_FERR# B6 H_IGNNE# B2 H_SMI# B5 H_PWRGD AB23 H_STPCLK# Y4 H_DPSLPR# AD25 H_INTR D1 H_NMI E5 H_INIT# W5 H_RESET# AB25
<18> H_A20M# <18> H_FERR# <18> H_IGNNE# <18> H_SMI# <18> H_PWRGD <18> H_STPCLK#
+CPU_CORE PM_CPUPERF# <19>
For Mobile
DP#0 DP#1 DP#2 DP#3
GND
VID0 VID1 VID2 VID3 VID4
2
H_TRDY#
RS#0 RS#1 RS#2 RSP# TRDY#
AE5 AE4 AE3 AE2 AE1
For Mobile
<9>
F1 G5 F4 AB2 J6
F8 G21 G24 G3 G6 J2 J22 J25 J5 K21 K24 K3 K6 L1 L23 L26 L4 M2 M22 M25 M5 N21 N24 N3 N6 P2 P22 P25 P5 R1 R23 R26 R4 T21 T24 T3 T6 U2 U22 U25 U5 V1 V23 V26 V4 W21 W24 W3 W6 Y2 Y22 Y25 Y5
H_BSEL0 2 1.5K_0402_5%
1 R19
H_RS#0 H_RS#1 H_RS#2
VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181
+3VS
<9> <9> <9>
2 56_0402_5%
2 PM_CPUPERF# @0_0402_5%
1 R317
VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 SKTOCC# VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128
U19B
AE11 AE13 AE15 AE17 AE19 AE22 AE24 AE26 AE7 AE9 AF1 AF10 AF12 AF14 AF16 AF18 AF20 AF26 AF6 AF8 B10 B12 B14 B16 B18 B20 B23 B26 B4 B8 C11 C13 C15 C17 C19 C2 C22 C25 C5 C7 C9 D10 D12 D14 D16 D18 D20 D21 D24 D3 D6 D8 E1 E11 E13 E15 E17 E19 E23 E26 E4 E7 E9 F10 F12 F14 F16 F18 F2 F22 F25 F5
1 R318 H _GHI#
2
B
1
A
D
E
F
G
H
I
R ev 1B Sheet
6
of
J
47
A
B
C
D
E
F
Layout note :
H
+CPU_CORE
Layout note :
Place close t o CPU, Use 2~3 vias per PAD. Place .22uF caps underneath balls on solder side. Place 10uF caps on the peripheral near balls. Use 2~3 vias per PAD.
1
G
Place close to CPU power and gr ound pin as possible (<1inch)
1
+
For Desktop's CPU:
2
2
C407 10U_1206_6.3V7K
2
1
2
1 C391 10U_1206_6.3V7K
2
1 C63 10U_1206_6.3V7K
2
1 C65 10U_1206_6.3V7K
2
2
2
C412 10U_1206_6.3V7K
2
C376 10U_1206_6.3V7K
2
1 C290 10U_1206_6.3V7K
2
C294 10U_1206_6.3V7K
2
2
1
2
C406 10U_1206_6.3V7K
2
2
1 C400 10U_1206_6.3V7K
2
2
2
C266 330U_D_2.5VM 2
PLACE ON CPU SIDE
2
0.22U_0603_10V7K 1
1
C111
2 0.22U_0603_10V7K
1 C258 10U_1206_6.3V7K
+
C262 330U_D_2.5VM
C113
C117
2 0.22U_0603_10V7K
2
0.22U_0603_10V7K 1
1
C119
C120
2 0.22U_0603_10V7K
2
0.22U_0603_10V7K 1
1
C110
C112
2 0.22U_0603_10V7K
2
0.22U_0603_10V7K 1
1
C116
3
C118
2 0.22U_0603_10V7K
2
C293 10U_1206_6.3V7K +12VALW 3
2
1 C408 10U_1206_6.3V7K
1
+
C265 330U_D_2.5VM 2
0.22U_0603_10V7K 1 C104
1
C150 @470U_D4_2.5VM 2
1
+ C152 @330U_D2E_2.5VM 2
1 +CPU_CORE
C388 10U_1206_6.3V7K
+
C149 470U_D4_2.5VM 2
1
+
+CPU_CORE
1
1
+
2
C151 330U_D_2.5VM
1 C282 10U_1206_6.3V7K
C148 @470U_D4_2.5VM
+CPU_CORE
Please place these cap on the socket north side
3
1
C263 470U_D4_2.5VM 2
1
+
C259 470U_D4_2.5VM 2
1 1
+
C147 470U_D4_2.5VM 2
1
+
C352 470U_D4_2.5VM
+ 1
1
+
C261 470U_D4_2.5VM 2
1
+
ESR total=1.875m ohm C total=2590uF
+CPU_CORE
1
1
+
C371 470U_D4_2.5VM
+CPU_CORE
For Mobile's CPU: 1
1
+
C390 470U_D4_2.5VM
ESR total=0.75m ohm C total=6350uF
+CPU_CORE
1
J
For DT
1
2
Please place these cap in the socket cavity area
I
2
2
C257 10U_1206_6.3V7K
2
C402 10U_1206_6.3V7K
2
Fan1 Control circuit
Q29 SI2303DS_SOT23
1 C401 10U_1206_6.3V7K
4
+12VS 2 R376
1
+5VS
Q10 FMMT619_SOT23 C 2 B E
1 3.48K_0603_1%
1
C410 10U_1206_6.3V7K
1
1
C411 10U_1206_6.3V7K
1
D14 1SS355_SOD323
2
C291 10U_1206_6.3V7K
2
<30>
1
EN_FAN1
C99 10U_1206_6.3V7K
2
3
1
R385 13K_0603_1%
+
3 1 O
-
+5VFAN_1 JP12
1
C566 @1000P_0402_50V7K
4
Q12 2SA1036K_SOT23
2
U10 LMV321M7_SC70-5
D21
1 2 3
2
ACES_85205-0300
2
2
C405 10U_1206_6.3V7K
1
G
C403 10U_1206_6.3V7K
1
C578 0.1U_0402_16V4Z
1
P
5 2
5
1
2
1
2
1
2
+CPU_CORE
1
C574 0.1U_0402_16V4Z D22 +5VS 1N4148_SOT23
2
3
2
1
2
SUSP
1
1
<17,33>
2
+CPU_CORE
4
5
1N4148_SOT23 2
1 2 R340 10K_0402_5%
1
+3VS
Please place these cap on the socket south side R381 7.32K_0603_1%
+CPU_CORE
2
1 C122 10U_1206_6.3V7K
2
1 C121 10U_1206_6.3V7K
2
1 C356 10U_1206_6.3V7K
2
1 C62 10U_1206_6.3V7K
2
Fan2 Control circuit
C404 10U_1206_6.3V7K
Q8 @2SC2411K_SOT23 C 2 B E
+5VS
1
6 2 R11
6
D11 @1SS355_SOD323
3
+12VS
1 @3.48K_0603_1% 2
+CPU_CORE
1
1
FAN1_TACH <30>
1
EN_FAN2 2
+CPU_CORE
1
3
1
1
2
2
4
2 1
D6
2
U1 @LMV321M7_SC70-5
Q1 @2SA1036K_SOT23
+5VFAN_2 JP19 C235 @1000P_0402_50V7K
C68 10U_1206_6.3V7K
2
C66 10U_1206_6.3V7K
1 2 3
2
@ACES_85205-0300
@1N4148_SOT23 1
R6 @7.32K_0603_1%
1 R200
Q63 @SM05_SOT23
2 +3VS 10K_0402_5%
7
FAN2_TACH <30> 3
2
C64 10U_1206_6.3V7K
1
1 2
C409 10U_1206_6.3V7K
C234 @0.1U_0402_16V4Z
2
1
O -
2
R10 @13K_0603_1%
7
+
1
1
<30>
2
2
2
D20 @1N4148_SOT23
+5VS
C296 10U_1206_6.3V7K
3 1
2
1 C100 10U_1206_6.3V7K
1
2
1 C368 10U_1206_6.3V7K
5
2
1 C292 10U_1206_6.3V7K
P
2
1 C351 10U_1206_6.3V7K
G
1
Dell-Compal Confidential 8
Title
Compal Electronics, Inc.
8
SCHEMATIC, M/B LA-1452
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 401230 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom 星期五, 四月 25, 2003 Date:
A
B
C
D
E
F
G
H
I
R ev 1B Sheet
7
of
J
47
10
9
8
7
6
5
4
3
2
1
Mobile CPU MO/DT_CPU H
+3VS
<6,40> CPU_VID0 <6,40> CPU_VID1 <6,40> CPU_VID2 <6,40> CPU_VID3
G
<6,40> CPU_VID4
CPU_VID0
2 R260
1 1K_0402_5%
CPU_VID1
2 R259
1 1K_0402_5%
CPU_VID2
2 R258
1 1K_0402_5%
CPU_VID3
2 R257
1 1K_0402_5%
CPU_VID4
2 R256
1 1K_0402_5%
VID VCC 1.750V 1.700V 1.650V 1.600V 1.550V 1.500V 1.450V 1.400V 1.350V 1.300V 1.250V 1.200V 1.150V 1.100V 1.050V 1.000V 0.975V 0.950V 0.925V 0.900V 0.875V 0.850V 0.825V 0.800V 0.775V 0.750V 0.725V 0.700V 0.675V 0.650V 0.625V 0.600V
+CPU_CORE +CPU_CORE
F
1
2
1 C200 @10U_1206_6.3V7K
2
1 C199 @0.1U_0402_16V4Z
2
C560 @0.1U_0402_16V4Z
JP15
<6> ITP_BPM0 <6> ITP_BPM1 <6> ITP_PRDY# <6> ITP_PREQ# <6,9> H_RESET# <6> ITP_TCK <6> CLK_ITP <6> CLK_ITP#
E
1 C201 @2.2P_0402_16VCJ
1
1 3 5 7 9 11 13 15 17 19 21 23 25
2 4 6 8 10 12 14 16 18 20 22 24 K
2 4 6 8 10 12 14 16 18 20 22 24 26
2 1.5K_0603_1% 2 75_0603_1% 2 39_0603_1% 2 150_0603_1%
2 R373
1 @33_0402_5%
ITP_TDI <6> ITP_TMS <6> ITP_TRST# <6> ITP_TCK <6>
ITP_TDO
@2MM SMT KEY26 C198 @2.2P_0402_16VCJ
2
<6>
R304 27.4_0603_1% 2
2
AGP_BUSY# <16,19> H_ITP_DBR# <6>
1
1 3 5 7 9 11 13 15 17 19 21 23 25
1 R184 1 R183 1 R372 1 R310
ITP Debug Connector
D
4
3
1 2
1
Desktop CPU
0
0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 VRM output off
4
3
0 2
1
0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X 1
0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X 1
1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X 1
H
G
F
E
D
C
C +5VS
1
2
C394 @0.1U_0402_16V4Z
C482 @0.1U_0402_16V4Z
1
B
SDA SCL OS# GND
2
U23 VCC A0 A1 A2
8 7 6 5
1 2 3 4
<6,30> SMB_EC_DA2 <6,30> SMB_EC_CK2 1 R351
2 @1K_0402_5%
@LM75CIMMX-5_MSOP8
SDA SCL OS# GND
VCC A0 A1 A2
8 7 6 5
@LM75CIMMX-5_MSOP8
1 R308
2 @10K_0402_5%
+5VS
B 1
U25 1 2 3 4
<6,30> SMB_EC_DA2 <6,30> SMB_EC_CK2
Address:1001_000X
2
R306 @1K_0402_5%
Address:1001_000X
Dell-Compal Confidential A
Title
Compal Electronics, Inc.
A
SCHEMATIC, M/B LA-1452
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS 401230 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom 星期五, 四月 25, 2003 Date:
10
9
8
7
6
5
4
3
2
R ev 1B Sheet
8
of
1
47
3
H A#[3..31]
DD R_SDQS[0..7]
<12> DDR_SDQS[0..7] HD#[0..63] <5>
DDR_SDM[0..7]
<12> DDR_SDM[0..7] HA#[3..31] <5>
DDR_SMA[0..12]
<12,13> DDR_SMA[0..12]
U12A
D
C
B
T30 R33 R34 N34 R31 L33 L36 P35 J36 K34 K36 M30 M35 L34 K35 H36 G34 G36 J33 D35 F36 F34 E36 H34 F35 D36 H35 E33 E34 B35 G31 C36 D33 D30 D29 E31 D32 C34 B34 D31 G29 C32 B31 B32 B30 B29 E27 C28 B27 D26 D28 B26 G27 H26 B25 C24 B23 B24 E23 C22 G25 B22 D24 G23
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
L31 J34 E29 E25 N31 G33 C30 D25
<6,8> H_RESET#
D22
<6> <6> <6> <6> <6> <6> <6> <6>
K30 J31 D27 H24 H30 AD30 P30
<15> CLK_MCH_BCLK <15> CLK_MCH_BCLK# <11> MCH_GTLREF 1 C335 0.1U_0402_10V6K
1
1
2
2
HOST,HUB
HDSTBP0# HDSTBP1# HDSTBP2# HDSTBP3# HDSTBN0# HDSTBN1# HDSTBN2# HDSTBN3#
W31 AA33 AB30 V34 Y36 AC33 Y35 AA36 AC34 AB34 Y34 AB36 AC36 AC31 AF35 AD36 AD35 AE34 AD34 AE36 AF36 AE33 AF34 AG34 AG36 AE31 AH35 AG33 AG31
HADSTB0# HADSTB1#
AB35 AF30
H_ADSTB#0 <6> H_ADSTB#1 <6>
P36 M36 T36 T34 M34 U33 U31 N36 U36 V30 T35
H_HIT# <5> H_HITM# <5> H_ADS# <5> H_BNR# <5> H_BPRI# <5> H_BREQ0# <5> H_DBSY# <6> H_DEFER# <5> H_DRDY# <6> H_TRDY# <6> H_LOCK# <5>
C26 B33 C35 N33
H_DBI#3 H_DBI#2 H_DBI#1 H_DBI#0
<6> <6> <6> <6>
V36 AA31 W33 AA34 W35
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 HI[0..10]
<5> <5> <5> <5> <5> <18>
HIT# HITM# ADS# BNR# BPRI# BREQ0# DBSY# DEFER# DRDY# HTRDY# HLOCK# DINV3 DINV2 DINV1 DINV0 HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HI10 HI9 HI8 HI7 HI6 HI5 HI4 HI3 HI2 HI1 HI0 HI_STBS HI_STBF RS2# RS1# RS0#
AF2 AE2 AF3 AE5 AE4 AF4 AD8 AC5 AC7 AB8 AA7
HX_RCOMP HY_RCOMP HX_SWING HY_SWING HI_VREF HI_RCOMP HI_SWING
H I10 HI9 HI8 HI7 HI6 HI5 HI4 HI3 HI2 HI1 HI0
HUB_PSTRB <18> HUB_PSTRB# <18>
P34 U34 R36
H_RS#2 H_RS#1 H_RS#0
B28 V35 H28 Y30 AD3 AC2 AD2
DDR_CLK2# DDR_CLK2 DDR_CLK1# DDR_CLK1 DDR_CLK0# DDR_CLK0
DDR_CLK3 <13> DDR_CLK3# <13> DDR_CLK4 <13> DDR_CLK4# <13> DDR_CLK5 <13> DDR_CLK5# <13>
U12B
AD4 AC4
CPURST# HCLK HCLK# HD_VREF2 HD_VREF1 HD_VREF0 HA_VREF HCC_VREF
<12> <12> <12> <12> <12> <12>
HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31
HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31
<6> <6> <6>
R18 2 1 24.9_0603_1% HX_RCOMP 10 mil R263 2 1 10 mil HY_RCOMP 24.9_0603_1%
DDR_SDQ0 AN4 DDR_SDQ1 AP2 DDR_SDQ2 AT3 DDR_SDQ3 AP5 DDR_SDQ4 AN2 DDR_SDQ5 AP3 DDR_SDQ6 AR4 DDR_SDQ7 AT4 DDR_SDQ8 AT5 DDR_SDQ9 AR6 DDR_SDQ10 AT9 DDR_SDQ11 AR10 DDR_SDQ12 AT6 DDR_SDQ13 AP6 DDR_SDQ14 AT8 DDR_SDQ15 AP8 DDR_SDQ16 AP10 DDR_SDQ17 AT11 DDR_SDQ18 AT13 DDR_SDQ19 AT14 DDR_SDQ20 AT10 DDR_SDQ21 AR12 DDR_SDQ22 AR14 DDR_SDQ23 AP14 DDR_SDQ24 AT15 DDR_SDQ25 AP16 DDR_SDQ26 AT18 DDR_SDQ27 AT19 DDR_SDQ28 AR16 DDR_SDQ29 AT16 DDR_SDQ30 AP18 DDR_SDQ31 AR20 DDR_SDQ32 AR22 DDR_SDQ33 AP22 DDR_SDQ34 AP24 DDR_SDQ35 AT26 DDR_SDQ36 AT22 DDR_SDQ37 AT23 DDR_SDQ38 AT25 DDR_SDQ39 AR26 DDR_SDQ40 AP26 DDR_SDQ41 AT28 DDR_SDQ42 AR30 DDR_SDQ43 AP30 DDR_SDQ44 AT27 DDR_SDQ45 AR28 DDR_SDQ46 AT30 DDR_SDQ47 AT31 DDR_SDQ48 AR32 DDR_SDQ49 AT32 DDR_SDQ50 AR36 DDR_SDQ51 AP35 DDR_SDQ52 AP32 DDR_SDQ53 AT33 DDR_SDQ54 AP34 DDR_SDQ55 AT35 DDR_SDQ56 AN36 DDR_SDQ57 AM36 DDR_SDQ58 AK36 DDR_SDQ59 AJ36 DDR_SDQ60 AP36 DDR_SDQ61 AM35 DDR_SDQ62 AK35 DDR_SDQ63 AK34
SDQ_0 SDQ_1 SDQ_2 SDQ_3 SDQ_4 SDQ_5 SDQ_6 SDQ_7 SDQ_8 SDQ_9 SDQ_10 SDQ_11 SDQ_12 SDQ_13 SDQ_14 SDQ_15 SDQ_16 SDQ_17 SDQ_18 SDQ_19 SDQ_20 SDQ_21 SDQ_22 SDQ_23 SDQ_24 SDQ_25 SDQ_26 SDQ_27 SDQ_28 SDQ_29 SDQ_30 SDQ_31 SDQ_32 SDQ_33 SDQ_34 SDQ_35 SDQ_36 SDQ_37 SDQ_38 SDQ_39 SDQ_40 SDQ_41 SDQ_42 SDQ_43 SDQ_44 SDQ_45 SDQ_46 SDQ_47 SDQ_48 SDQ_49 SDQ_50 SDQ_51 SDQ_52 SDQ_53 SDQ_54 SDQ_55 SDQ_56 SDQ_57 SDQ_58 SDQ_59 SDQ_60 SDQ_61 SDQ_62 SDQ_63
D
BROOKDALE-GL/PE DDR
SMAA12/BS0 SMAA11/DQS8 SMAA10/DQ31 SMAA9/SMA3 SMAA8/SMA4 SMAA7/SMA6 SMAA6/SDQ29 SMAA5/SMA8 SMAA4/SMA11 SMAA3/SMA7 SMAA2/SMA9 SMAA1/SDQ19 SMAA0/SMA12 SMAB5 SMAB4 SMAB2 SMAB1
AN15 AL15 AK26 AK16 AN17 AP17 AP19 AL17 AL19 AK20 AP23 AN25 AL25 AK18 AN19 AN23 AP25
DDR_SMA12 DDR_SMA11 DDR_SMA10 DDR_SMA9 DDR_SMA8 DDR_SMA7 DDR_SMA6 DDR_SMA5 DDR_SMA4 DDR_SMA3 DDR_SMA2 DDR_SMA1 DDR_SMA0 DDR_SMAB5 DDR_SMAB4 DDR_SMAB2 DDR_SMAB1
SBA1 SBA0
AP27 AN27
DDR_SBS1 DDR_SBS0
SDQS0 SDQS1 SDQS2 SDQS3 SDQS4 SDQS5 SDQS6 SDQS7
AR2 AT7 AT12 AT17 AR24 AT29 AT34 AL36
DDR_SDQS0 DDR_SDQS1 DDR_SDQS2 DDR_SDQS3 DDR_SDQS4 DDR_SDQS5 DDR_SDQS6 DDR_SDQS7
SDM0 SDM1 SDM2 SDM3 SDM4 SDM5 SDM6 SDM7
AP4 AR8 AP12 AR18 AT24 AP28 AR34 AL34
DDR_SDM0 DDR_SDM1 DDR_SDM2 DDR_SDM3 DDR_SDM4 DDR_SDM5 DDR_SDM6 DDR_SDM7
AL13 AK14 AN13 AP13
DDR_CKE3 DDR_CKE2 DDR_CKE1 DDR_CKE0
AL29 AP31 AK30 AN31
DDR_SCS#0 DDR_SCS#1 DDR_SCS#2 DDR_SCS#3
AK28 AN29 AP29
DDR_SRAS# DDR_SCAS# DDR_SWE#
AK24 AL23
RDCLKO R DCLKI
SCKE3/SCK#5 SCKE2/RSVD SCKE1/SDQ58 SCKE0/RSVD SCS#0/SCKE2 SCS#1/RSVD SCS#2/SCK#2 SCS#3/SCAS# SRAS#/SCKE0 SCAS#/RSVD SWE#/SDQ5 SRCVEN_OUT# SRCVEN_IN# SMY_RCOMP SM_VREF
DDR_SMAB5 DDR_SMAB4 DDR_SMAB2 DDR_SMAB1
<13> <13> <13> <13>
DDR_SBS1 <12,13> DDR_SBS0 <12,13>
C
DDR_CKE3 DDR_CKE2 DDR_CKE1 DDR_CKE0 DDR_SCS#0 DDR_SCS#1 DDR_SCS#2 DDR_SCS#3
<13> <13> <12> <12> <12> <12> <13> <13>
DDR_SRAS# <12,13> DDR_SCAS# <12,13> DDR_SWE# <12,13> 2 R297
1 @0_0603_5%
RDCLKI & RDCLKO 100mils LENGTH 5mils WIDTH
AJ34
2
AM2
1 1
2
BROOKDALE-GL/PE_760P
2
B
+2.5V
R298 60.4_0603_1%
SDREF
R299 0_0603_5%
1
C364 0.1U_0402_10V6K
R292 60.4_0603_1%
1
C357 0.1U_0402_10V6K
2
H_XY_SWING <11> HUB_VREF <11,18> 2 +1.5VS 68_0603_1% HUB_VSWING <11,18>
1 R295
C274 BROOKDALE-GL/PE_760P
C304 2
BROOKDALE-GL/PE HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
2
HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
1
AL21 AK22 AN11 AP11 AM34 AL33 AP21 AN21 AP9 AN9 AP33 AN34
HD#[0..63]
2
DD R_SDQ[0..63]
<12> DDR_SDQ[0..63]
1
4
SCMD_CLK0 SCMD_CLK0# SCMD_CLK1 SCMD_CLK1# SCMD_CLK2 SCMD_CLK2# SCMD_CLK3 SCMD_CLK3# SCMD_CLK4 SCMD_CLK4# SCMD_CLK5 SCMD_CLK5#
5
0.1U_0402_10V6K
1
82845GL-INT VGA 0.1U_0402_10V6K
82845PE-EXT VGA
2
1 C302 0.1U_0402_10V6K
Close to H28
2
C327 0.1U_0402_10V6K
Close to Y30
A
A
Layout note :
1. HX_RCOMP, HY_RCOMP Trace width 10 mil. 2. Terminator Max 500 mil.
Dell-Compal Confidential Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date:
5
4
3
2
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet 1
9
of
47
B
C
D
+1.5VS
AGP_AD[0..31] AGP_SBA[0..7]
Place close to pin D14 +2.5V
ANALOG DISPLAY
1
2
2
R241 36.5_0603_1%
2
2 INTCRT_B <16> +CPU_CORE
INTCRT_G <16>
1
INTCRT_R <16>
BROOKDALE-GL/PE_760P
R273 8.2K_0402_5%
C324 0.1U_0402_10V6K 2
1
R17 137_0603_1%
CLK_MCH_DISPLAY <15> PM_PWROK <19,30,32> H_SEL0 <15>
R270 1 2 8.2K_0402_5% INTCRT_B INTCRT_B# INTCRT_G INTCRT_G# INTCRT_R INTCRT_R#
G15 H16 E15 F16 C15 D16
BLUE BLUE# GREEN GREEN# RED RED#
CLK_MCH_66M <15>
RSTIN#
PSBSEL *
FSB FREQUENCY
0
400 MHZ
1
533 MHZ
C
B18 C18 D18 H18 B19 C19 D19 E19 G19 J19 B20 C20 D20 F20 H20 F18 K18 K20 K22 K26 M28 T28 Y28 AD28
VTTFSB0 VTTFSB1 VTTFSB2 VTTFSB3 VTTFSB4 VTTFSB5 VTTFSB6 VTTFSB7 VTTFSB8 VTTFSB9 VTTFSB10 VTTFSB11 VTTFSB12 VTTFSB13 VTTFSB14 VTTFSB15 VTTFSB16 VTTFSB17 VTTFSB18 VTTFSB19 VTTFSB20 VTTFSB21 VTTFSB22 VTTFSB23
R277 L3 KC FBM-L11-201209-221LMAT_0805 VCCA_DPLL 1 2 1 1 1 + C29 C22 22U_1206_10V4Z 150U_D2_6.3VM 2 2 2
+1.5VS
R43 0_0402_5% 2 1
RSTIN#
1
PCIRST#
2
C251 0.1U_0402_10V6K
L4 KC FBM-L11-201209-221LMAT_0805 VCCA_FSB 1 2
+1.5VS
1 C27 0.1U_0402_10V6K
2
1
2
1 C28 22U_1206_10V4Z
2
1
AB2 Y2
1.5K_0402_5%
<6,16,18,22,23,25,26,30,33>
2
C69 @15P_0402_50V8J
+1.5VS
C33 0.1U_0402_10V6K
A37 AB3 AA2 AA3 AA4 AA5 Y4 Y8 W7 AU37 AU36 AT37 AU2 AU1 AT1 AJ35 AH34
A3 A7 C1 D4 D6 G1 K6 L1 L9 P6 R1 R9 W9 V6 P10 V10 AB10
BROOKDALE-GL/PE POWER
VCCA_SM0 VCCA_SM1 VCCQSM0 VCCQSM1 VCCQSM2 VTTDECAP0 VTTDECAP1 VTTDECAP2 VTTDECAP3 VTTDECAP4
TESTIN# MEM_SEL
VCCA_FSB
RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8
VCCA_HI VCCHI0 VCCHI1 VCCHI2 VCCHI3 VCCA_DPLL VCCGPIO VCCA_DAC0 VCCA_DAC1
NC NC NC NC NC NC NC NC
SMX_RCOMP NC NC NC NC
2
2
2
100U_D2_6.3VM
L27 KC FBM-L11-201209-221LMAT_0805 B
+1.5VS
1
1
2
C334 4.7U_0805_10V4Z
2
R281 1_0402_5%
AG1 AG2
VCCA_SM 1
0.1U_0402_10V6K 1 1
AT20 AT21 AU21
C640
C353
A31 AC37 R37 L37 G37 A17
2
VCCA_DAC 1
2
1
2
+ C336 100U_D2_6.3VM
2
2 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K C
VCCA_FSB
1
1 C277
AD10 AD6 AC9 AC1 AE3 A13 B6 B14 A15
A
C159 100U_D2_6.3VM
2 +1.5VS
1 C297
2
0.1U_0402_10V6K
1 C316
2
1 C332
C32
2
0.1U_0402_10V6K
2 0.1U_0402_10V6K
VCCA_DPLL +3VS VCCA_DAC
1
AF10
2
A2 A36 B37 B1
R287 60.4_0603_1%
1
R283 60.4_0603_1%
+2.5V 2
C270 0.1U_0402_10V6K
1
2
C344 0.1U_0402_10V6K
2
BROOKDALE-GL/PE_760P
+ C399
C267
HSYNC VSYNC DDCA_CLK DDCA_DATA REFSET
1
<16> INT_HSYNC <16> INT_VSYNC <16> INTDDCCK <16> INTDDCDA
B7 C6 D7 C7 B16
2
1
+ C340
0.01U_0402_25V4Z
47.5_0603_1% R215 1 2 1 2 R214 47.5_0603_1%
1
100U_D2_6.3VM 1
+
C268
L2 W2
+AGPREF
AE7 AJ31 D14 E7 Y3
C333 10P_0402_50V8K
1
0.1U_0402_10V6K
AGP_C/BE#3 AGP_C/BE#2 AGP_C/BE#1 AGP_C/BE#0
R286 22_0402_5%
AH8 AK8 AG9 AJ9 AL9 AM22 AJ23 AL37 AU9 AK10 AJ11 AL11 AU25 AM26 AU13 AM14 AJ27 AJ1 AL1 AJ15 AP15 AU29 AH2 AJ2 AK2 AL2 AM30 AH3 AJ3 AK3 AL3 AH4 AJ4 AK4 AL4 AU17 AJ5 AL5 AU5 AM18 AJ19 AK32 AU33 AH6 AK6 AP20 AG7 AJ7 AL7 AP7 AH10 AH12 AH14 AH18 AH22 AH26
1
M4 N7 N5 P2 N2 D5 P4 B5 H2 M2 N4 R4
CLK_MCH_66M
VCCSM0 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8 VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36 VCCSM37 VCCSM38 VCCSM39 VCCSM40 VCCSM41 VCCSM42 VCCSM43 VCCSM44 VCCSM45 VCCSM46 VCCSM47 VCCSM48 VCCSM49 VCCSM50 VCCSM51 VCCSM52 VCCSM53 VCCSM54 VCCSM55
2
<16> AGP_FRAME# <16> AGP_IRDY# <16> AGP_TRDY# <16> AGP_STOP# <16> AGP_DEVSEL# <16> AGP_REQ# <16> AGP_PAR <16> AGP_GNT# <16> AGP_C/BE#3 <16> AGP_C/BE#2 <16> AGP_C/BE#1 <16> AGP_C/BE#0
Place close to pin AE7
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43
L28 KC FBM-L11-201209-221LMAT_0805
V8 U7 M8 L7 F4 E5
2
Y19 AA19 W20 U21 W21 AA21 A9 B9 C9 D9 E9 B10 C10 D10 F10 H10 A11 B11 C11 D11 E11 G11 J11 B12 C12 D12 F12 H12 G13 J13 H14 J15 AA17 W17 U17 W18 V19 U19 K10 K12 K14 K16 W19
1
<16> AGP_ADSTB0 <16> AGP_ADSTB0# <16> AGP_ADSTB1 <16> AGP_ADSTB1# <16> AGP_SBSTB <16> AGP_SBSTB#
1
2
C4 B4 B3
C249 5P_0402_50V8C
1
B
AGP_ST0 AGP_ST1 AGP_ST2
AGP_ST0 AGP_ST1 AGP_ST2
R234 10_0402_5%
AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31
V4 V2 W4 W5 U5 U4 U2 V3 T2 T3 T4 R2 R5 R7 T8 P3 P8 K4 K2 J2 M3 L5 L4 H4 G2 K3 J4 J5 J7 H3 K8 G4
GAD0/DVOBHSYNC GAD1/DVOBVSYNC GAD2/DVOBD1 GAD3/DVOBD0 GAD4/DVOBD3 GAD5/DVOBD2 GAD6/DVOBD5 GAD7/DVOBD4 GAD8/DVOBD6 GAD9/DVOBD9 GWBF# GAD10/DVOBD8 GRBF# GAD11/DVOBD11 BROOKDALE-GL/PE GAD12/DVOBD10 GST0 GAD13/DVOBCCLKINT# GST1 GAD14/DVOBFLDSTL GST2 GAD15/MDDC CLK GAD16/DVOCVSYNC GAD_STB0/DVOBCLK GAD17/DVOCHSYNC GAD_STB0#/DVOBCLK# GAD18/DVOCBLANK# GAD_STB1/DVOCCLK GAD19/DVOCD0 GAD_STB1#/DVOCCLK# GAD20/DVOCD1 GSBSTB GAD21/DVOCD2 GSBSTB# GAD22/DVOCD3 GAD23/DVOCD4 G_FRAME#/MDVI DATA GAD24/DVOCD7 G_IRDY#/MI2C CLK GAD25/DVOCD6 G_TRDY#/MDVI CLK GAD26/DVOCD9 G_STOP#/MDDC DATA GAD27/DVOCD8 G_DEVSEL#/MI2C DATA GAD28/DVOCD11 G_REQ# GAD29/DVOCD10 G_PAR/ADD_DETECT GAD30/DVOBCINTR# G_GNT# GAD31/DVOCFLDSTL GCBE3#/DVOCD5 GCBE2# GCBE1#/DVOBBLANK# GCLKIN GCBE0#/DVOBD7 RSTIN# DREFCLK AGP RCOMP/DVOBCRCOMP PWROK AGP_VREF PSBSEL
2
<16> <16> <16>
AGP/DVO
C385
G5 G7
<16> AGP_WBF# <16> AGP_RBF#
GPIPE# GSBA0/ADDIN0 GSBA1/ADDIN1 GSBA2/ADDIN2 GSBA3/ADDIN3 GSBA4/ADDIN4 GSBA5/ADDIN5 GSBA6/ADDIN6 GSBA7/ADDIN7
1
A
H8 C3 C2 D3 D2 E4 E2 F3 F2
2
AGP_PIPE# AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7
<16> AGP_PIPE#
U12D
VCCAGP0 VCCAGP1 VCCAGP2 VCCAGP3 VCCAGP4 VCCAGP5 VCCAGP6 VCCAGP7 VCCAGP8 VCCAGP9 VCCAGP10 VCCAGP11 VCCAGP12 VCCAGP13 VCCAGP14 VCCAGP15 VCCAGP16
1
CLK_MCH_DISPLAY U12C
0.1U_0402_10V6K
<16> AGP_AD[0..31] <16> AGP_SBA[0..7]
E
1
A
INTCRT_B# INTCRT_G#
+1.5VS
INTCRT_R#
1
D
2
1 C343 0.1U_0402_10V6K
2
C341 0.1U_0402_10V6K
D
NEAR AA1 NEAR AE1
Dell-Compal Confidential Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
10
of
47
5
4
3
2
1
HUB_VSWING <9,18>
1
R264 226_0603_1% 2
0.01U_0402_25V4Z
1
R312 100_0603_1% 2
BROOKDALE-GL/PE_760P
VSSA_DAC0 VSSA_DAC1
NEAR MCH
2
0.1U_0402_10V6K
NEAR ICH
NEAR MCH
Within 250mil
1
2
C125 0.01U_0402_25V4Z
NEAR ICH
D
Within 250mil
10 mil Trace, 7 mil Space
1 R245
+CPU_CORE
2 49.9_0603_1%
MCH_GTLREF <9> 1
R244 100_0603_1%
C299 0.1U_0402_10V6K
2
2
FSB DECOUPLING
+CPU_CORE
NEAR MCH 10U_1206_6.3V7K 1
0.1U_0402_10V6K
1 C245
1 C246
2
1 C255
2
10U_1206_6.3V7K
0.1U_0402_10V6K
1 C253
2
1 C254
2
1 C252
2
0.1U_0402_10V6K
2
C250 0.1U_0402_10V6K
2
10 mil Trace, 7 mil Space
0.1U_0402_10V6K R246 2
+CPU_CORE
1
H_XY_SWING <9>
301_0603_1% 0.1U_0402_10V6K 1
1 C281
2
1 C279
2
2
0.1U_0402_10V6K
R247 150_0603_1%
1 C284
2
2
C
1
0.1U_0402_10V6K
1 C288
C289 0.1U_0402_10V6K
C309 0.01U_0402_25V4Z
2
0.1U_0402_10V6K
SYSTEM MEMORY DECOUPLING +2.5V 0.1U_0402_10V6K 1
1 C345
0.1U_0402_10V6K 1
C346
2
1
1 C367
1
0.1U_0402_10V6K
1 C380
2
1
0.1U_0402_10V6K
1 C383
2
1 C384
2
0.1U_0402_10V6K
1
1
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1 C338
2
1 C354
2
0.1U_0402_10V6K
2
0.1U_0402_10V6K
C366
2
C358
2
0.1U_0402_10V6K
C382
2
1 C361
2
0.1U_0402_10V6K
C381
2
1 C374
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1 C373
2
0.1U_0402_10V6K
0.1U_0402_10V6K 1
C362
2
0.1U_0402_10V6K
C379
2
1 C363
2
0.1U_0402_10V6K
0.1U_0402_10V6K 1
C347
2
0.1U_0402_10V6K
C378
2
1 C359
2
0.1U_0402_10V6K
0.1U_0402_10V6K 1
C370
2
0.1U_0402_10V6K
C360 2
1 C350
2
0.1U_0402_10V6K 1
1 C349
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1 C348
2
2
2
B
C365 0.1U_0402_10V6K
0.1U_0402_10V6K
GMCH DECOUPLING +1.5VS 0.1U_0402_10V6K 1
1 C326
B15 C14
2
1
1
2
1
R309 C392 PLACE NOTE: C339 CAP PLACE 0.1U_0402_10V6K AT MIDPOINT 2 2 OF THE BUS. 100_0603_1%
2
C17 B17 AM16 W3 U3 R3 D17 N3 L3 J3 G3 E3 AT2 F30 AR29 AJ29 AG29 AE29 AC29 AA29 W29 R29 U29 N29 L29 J29 C29 A29 AU15 AR15 D15 B2 AR1 AN1 AE1 AA1 U1 N1 J1 E1 AM28 F28 AU27 AR27 AL27 F14 AR13 AJ13 J27 C27 A27 E13 D13 C13 B13 AM12 AK12 F26 AR25 AJ25 J25 AU11 AR11 AR37 AN37 C25 AJ37 AG37 AE37 AA37 U37 AH28 AF28 AB28 V28 P28 K28 K24 J37 E37 C37 AT36 AH36
1
1
VSS
VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211
1 C393
AR9 AR17 AJ17 Y17 AG4 AB4 AU3 AR3 AN3 AM3 AG3 AC3 C31 AH30 V17 J17 G17 E17
BROOKDALE-GL/PE
VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110
B
VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85
C126
0.1U_0402_10V6K 1
C329
2
1 C322
2
C331
2
0.1U_0402_10V6K
0.1U_0402_10V6K 1
2
0.1U_0402_10V6K
1 C308
0.1U_0402_10V6K 1
C330
2
1 C328
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K 1
C271 2
1 C278
C298
2
0.1U_0402_10V6K
0.1U_0402_10V6K 1
2
1 C256
2
0.1U_0402_10V6K
1 C342
C280
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
N35 R35 U35 AA35 AC35 AE35 AG35 AL35 AN35 AR35 AU35 B36 W36 AF8 AM8 G9 J9 N9 U9 AA9 AE9 A23 C23 D23 J23
C
VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128
U12E AM10 AR23 AU23 F24 AM24 A25 C16 N37 U18 V18 Y18 AA18 AL31 AR31 AU31 F32 H32 K32 M32 P32 T32 V32 Y32 AB32 AD32 AF32 AH32 AM4 A5 C5 AG5 AN5 AR5 AR19 AM32 A33 C33 AJ33 AN33 AR33 F6 H6 M6 T6 Y6 AB6 AF6 AM6 U20 V20 Y20 AA20 AM20 A21 B21 C21 D21 E21 G21 J21 D34 W34 A35 E35 G35 J35 L35 AN7 AR7 AU7 B8 C8 D8 F8 V21 Y21 AJ21 AR21 F22 H22 M10 T10 Y10 AH16 AH20 AH24
HUB_VREF <9,18>
2
1 C337 0.01U_0402_25V4Z
D
10 mil Trace, 7 mil Space
0.01U_0402_25V4Z 1
+1.5VS
0.1U_0402_10V6K 1
1 C301
2
0.1U_0402_10V6K 1
C300 2
1 C285
2
0.1U_0402_10V6K 1
C269 2
1 C276
2
0.1U_0402_10V6K 1
C275 2
1 C260
2
0.1U_0402_10V6K 1
C307 2
1 C295
0.1U_0402_10V6K 1
C287
2
2
1 C311
2
1 C286
C283
2
2
A
A
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
Dell-Compal Confidential Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5
4
3
2
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet 1
11
of
47
A
B
C
D
E
F
G
H
+2.5V
DDR_SDQ4 DDR_SDQ0
RP32 1 2
10_4P2R_0402_5% DDR_DQ4 4 DDR_DQ0 3
DDR_SDQ30 DDR_SDQ26
RP46 1 2
RP42 DDR_SDQ1 1 DDR_SDQ5 2
10_4P2R_0402_5% DDR_DQ1 4 DDR_DQ5 3
RP37 DDR_SDQ31 1 DDR_SDQ27 2
RP33 1 2
10_4P2R_0402_5% DDR_DQ6 4 DDR_DQ2 3
DDR_SDM0 DDR_SDM1
R124 2 2 R117
10_0402_5% DDR_DM0 1 DDR_DM1 1 10_0402_5%
RP43 DDR_SDQ3 1 DDR_SDQ7 2
10_4P2R_0402_5% DDR_DQ3 4 DDR_DQ7 3
R126 DDR_SDM2 2 DDR_SDM3 2 R121
10_0402_5% DDR_DM2 1 DDR_DM3 1 10_0402_5%
DDR_SDQ9 DDR_SDQ8
RP20 1 2
10_4P2R_0402_5% DDR_DQ9 4 DDR_DQ8 3
DDR_SDM4 DDR_SDM5
R108 2 2 R113
10_0402_5% DDR_DM4 1 DDR_DM5 1 10_0402_5%
DDR_SDQ13 DDR_SDQ12
RP31 1 2
10_4P2R_0402_5% DDR_DQ13 4 DDR_DQ12 3
DDR_SDM6 DDR_SDM7
R115 2 2 R118
10_0402_5% DDR_DM6 1 DDR_DM7 1 10_0402_5%
DDR_SDQ6 DDR_SDQ2 1
JP22 DDR_DQ5 DDR_DQ1
10_4P2R_0402_5% DDR_DQ31 4 DDR_DQ27 3
DDR_DQS0 DDR_DQ2 DDR_DQ6 DDR_DQ8 DDR_DQ9 DDR_DQS1 DDR_DQ14 DDR_DQ15 <9> DDR_CLK1 <9> DDR_CLK1#
DDR_DQ20 DDR_DQ16 DDR_DQS2 DDR_DQ18 DDR_DQ22 DDR_DQ24 DDR_DQ28 DDR_DQS3
DDR_SDQ15 DDR_SDQ14
RP21 1 2
10_4P2R_0402_5% DDR_DQ15 4 DDR_DQ14 3
DDR_SDQ37 DDR_SDQ32
RP16 1 2
10_4P2R_0402_5% DDR_DQ37 4 DDR_DQ32 3
DDR_SDQ11 DDR_SDQ10
RP40 1 2
10_4P2R_0402_5% DDR_DQ11 4 DDR_DQ10 3
DDR_SDQ36 DDR_SDQ33
RP28 1 2
10_4P2R_0402_5% DDR_DQ36 4 DDR_DQ33 3
DDR_SDQ16 DDR_SDQ20
RP41 1 2
10_4P2R_0402_5% DDR_DQ16 4 DDR_DQ20 3
DDR_SDQ38 DDR_SDQ34
RP26 1 2
10_4P2R_0402_5% DDR_DQ38 4 DDR_DQ34 3
DDR_SDQ21 DDR_SDQ17
RP35 1 2
10_4P2R_0402_5% DDR_DQ21 4 DDR_DQ17 3
DDR_SDQ35 DDR_SDQ39
RP15 1 2
10_4P2R_0402_5% DDR_DQ35 4 DDR_DQ39 3
DDR_SDQ22 DDR_SDQ18
RP44 1 2
10_4P2R_0402_5% DDR_DQ22 4 DDR_DQ18 3
DDR_SDQ44 DDR_SDQ40
RP27 1 2
10_4P2R_0402_5% DDR_DQ44 4 DDR_DQ40 3
DDR_SDQ23 DDR_SDQ19
RP34 1 2
10_4P2R_0402_5% DDR_DQ23 4 DDR_DQ19 3
DDR_SDQ41 DDR_SDQ45
RP17 1 2
10_4P2R_0402_5% DDR_DQ41 4 DDR_DQ45 3
DDR_SDQ28 DDR_SDQ24
RP45 1 2
10_4P2R_0402_5% DDR_DQ28 4 DDR_DQ24 3
DDR_SDQ46 DDR_SDQ42
RP29 1 2
10_4P2R_0402_5% DDR_DQ46 4 DDR_DQ42 3
DDR_SDQ25 DDR_SDQ29
RP38 1 2
10_4P2R_0402_5% DDR_DQ25 4 DDR_DQ29 3
DDR_SDQ47 DDR_SDQ43
RP22 1 2
10_4P2R_0402_5% DDR_DQ47 4 DDR_DQ43 3
2
DDR_DQ26 DDR_DQ30
<9> DDR_CLK0 <9> DDR_CLK0# <9>
DDR_CKE1
DDR_CKE1 DDR_SMAA12 DDR_SMAA9 DDR_SMAA7 DDR_SMAA5 DDR_SMAA3 DDR_SMAA1
<9> DDR_SCS#0
DDR_SMAA10 DDR_BS0 DDR_WE# DDR_SCS#0 DDR_DQ33 DDR_DQ36 DDR_DQS4 DDR_DQ34 DDR_DQ38 DDR_DQ40 DDR_DQ44 DDR_DQS5
3
<9> DDR_SDQ[0..63] <9> DDR_SDQS[0..7] <9,13> DDR_SMA[0..12] <9> DDR_SDM[0..7]
DD R_SDQ[0..63] DD R_SDQS[0..7]
DDR_SDQ49 DDR_SDQ48
RP30 1 2
10_4P2R_0402_5% DDR_DQ49 4 DDR_DQ48 3
DDR_SDQ53 DDR_SDQ52
RP18 1 2
10_4P2R_0402_5% DDR_DQ53 4 DDR_DQ52 3
DDR_DQ42 DDR_DQ46
DDR_SMA[0..12] DDR_SDM[0..7]
DDR_SDQ57 DDR_SDQ61
RP51 1 2
10_4P2R_0402_5% DDR_DQ57 4 DDR_DQ61 3
DDR_SDQ55 DDR_SDQ54
RP25 1 2
10_4P2R_0402_5% DDR_DQ55 4 DDR_DQ54 3
DDR_SDQ56 DDR_SDQ60
RP50 1 2
10_4P2R_0402_5% DDR_DQ56 4 DDR_DQ60 3
DDR_SDQ50 DDR_SDQ51
RP23 1 2
10_4P2R_0402_5% DDR_DQ50 4 DDR_DQ51 3
DDR_SDQ58 DDR_SDQ63
RP36 1 2
10_4P2R_0402_5% DDR_DQ58 4 DDR_DQ63 3
DDR_SDQ59 DDR_SDQ62
RP39 1 2
10_4P2R_0402_5% DDR_DQ59 4 DDR_DQ62 3
SDREF_DIMM
+2.5V
10_4P2R_0402_5% DDR_DQ30 4 DDR_DQ26 3
DDR_DQ48 DDR_DQ49 DDR_DQS6 DDR_DQ54 DDR_DQ55 DDR_DQ60 DDR_DQ56 DDR_DQS7 DDR_DQ63 DDR_DQ58 <13,15,18,26> DIMM_SMDATA <13,15,18,26> DIMM_SMCLK +3VS
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
R322
VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS
VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS
DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 CK2# VDD CKE1 DU/A13 A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 WE# S0# DU VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDD_SPD VDD_ID
DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU/RESET# VSS VSS VDD VDD CKE0 DU/BA2 A11 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# S1# DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
20mil DDR_DQ0 DDR_DQ4 DDR_DM0 DDR_DQ7
DDR_SDQS0 DDR_SDQS1 DDR_SDQS2 DDR_SDQS3
2 R119 2 R109 2 R120 2 R127
DDR_DQS0 1 10_0402_5% DDR_DQS1 1 10_0402_5% DDR_DQS2 1 10_0402_5% DDR_DQS3 1 10_0402_5%
DDR_SDQS4 DDR_SDQS5 DDR_SDQS6 DDR_SDQS7
2 R114 2 R106 2 R107 2 R129
DDR_DQS4 1 10_0402_5% DDR_DQS5 1 10_0402_5% DDR_DQS6 1 10_0402_5% DDR_DQS7 1 10_0402_5%
Layout note Place these resistors close to DIMM0, all trace length<500 mil
2
1
SDREF
0_0402_5% DDR _DQ[0..63]
C413 0.1U_0402_16V4Z
DDR_DQ[0..63] <13>
DDR _DQS[0..7]
DDR_DQS[0..7] <13>
D DR_DM[0..7] DDR_DQ3 DDR_DQ12
DDR_DM[0..7] <13>
DDR_SMAA[0..12]
DDR_SMAA[0..12] 1
DDR_DQ13 DDR_DM1 DDR_DQ10 DDR_DQ11
DDR_SMA0 2 R167 DDR_SMA1 2 R134 DDR_SMA2 2 R132 DDR_SMA3 2 R149 DDR_SMA4 2 R135 DDR_SMA5 2 R140 DDR_SMA6 2 R152 DDR_SMA7 2 R116 DDR_SMA8 2 R137 DDR_SMA9 2 R148 DDR_SMA10 2 R146 DDR_SMA11 2 R151 DDR_SMA12 2 R136
DDR_DQ17 DDR_DQ21 DDR_DM2 DDR_DQ19 DDR_DQ23 DDR_DQ29 DDR_DQ25 DDR_DM3 DDR_DQ27 DDR_DQ31
DDR_SMAA0 1 10_0402_5% DDR_SMAA1 1 10_0402_5% DDR_SMAA2 1 10_0402_5% DDR_SMAA3 1 10_0402_5% DDR_SMAA4 1 10_0402_5% DDR_SMAA5 1 10_0402_5% DDR_SMAA6 1 10_0402_5% DDR_SMAA7 1 10_0402_5% DDR_SMAA8 1 10_0402_5% DDR_SMAA9 1 10_0402_5% DDR_SMAA10 1 10_0402_5% DDR_SMAA11 1 10_0402_5% DDR_SMAA12 1 10_0402_5%
2
Note: Place Close to DIMM0 DDR_CKE0
DDR_CKE0 <9>
DDR_SMAA11 DDR_SMAA8
Layout note
DDR_SMAA6 DDR_SMAA4 DDR_SMAA2 DDR_SMAA0 DDR_BS1 DDR_RAS# DDR_CAS# DDR_SCS#1
Place these resistor close by DIMM0, all trace length Max=1.4" DDR_SCS#1 <9> +1.25VS
DDR_DQ32 DDR_DQ37 DDR_DM4 DDR_DQ39
RP47 DDR_CKE0 1 DDR_CKE1 2
DDR_DQ35 DDR_DQ45
4 3
56_4P2R_0402_5%
DDR_DQ41 DDR_DM5
3
RP49 DDR_SCS#0 1 DDR_SCS#1 2
DDR_DQ43 DDR_DQ47
4 3
56_4P2R_0402_5% DDR_CLK2# <9> DDR_CLK2 <9> DDR_DQ52 DDR_DQ53 DDR_DM6 DDR_DQ51 DDR_DQ50 DDR_DQ61 DDR_DQ57 DDR_DM7
Note: Place Close to DIMM0
DDR_DQ62 DDR_DQ59
2 R139 2 R133 2 R141 2 R131 2 R138
<9,13> DDR_SBS0 <9,13> DDR_SBS1 <9,13> DDR_SRAS# <9,13> DDR_SCAS#
JAE MM50-200B1-1R_200P_Reverse 4
2 1
<9,13> DDR_SWE#
1 10_0402_5% 1 10_0402_5% 1 10_0402_5% 1 10_0402_5% 1 10_0402_5%
DDR_BS0 DDR_BS1 DDR_RAS# DDR_CAS# DDR_WE# 4
DIMM0 Dell-Compal Confidential Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
E
F
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003 G
Sheet
12 H
of
47
A
B
+1.25VS
C
D
E
+2.5V
+2.5V
+1.25VS
SDREF_DIMM JP23
RP89
1
RP103
DDR_DQ4 DDR_DQ0
1 2
DDR_DQ5 DDR_DQ1
56_4P2R_0402_5% RP109 1 4 2 3
56_4P2R_0402_5% RP82 4 1 DDR_DQ27 3 2 DDR_DQ31
56_4P2R_0402_5% RP70 4 1 DDR_DQ53 3 2 DDR_DQ52
56_4P2R_0402_5% RP88 DDR_DQS0 1 4 DDR_DQ6 2 3
56_4P2R_0402_5% RP69 4 1 DDR_DQ56 3 2 DDR_DQ51
56_4P2R_0402_5% RP95 4 1 DDR_DQ54 3 2 DDR_DQS6
4 3
4 3
DDR_DQ26 DDR_DQ30
1 2
4 3
4 3
56_4P2R_0402_5% RP94 1 DDR_DQ60 2 DDR_DQ57
1 2
56_4P2R_0402_5% RP108 4 3
4 3
56_4P2R_0402_5% RP68 1 DDR_DQ61 2 DDR_DQS7
DDR_DQ9 1 DDR_DQ12 2
56_4P2R_0402_5% RP87 4 3
4 3
56_4P2R_0402_5% RP93 1 DDR_DQ62 2 DDR_DQ58
DDR_DQS1 1 DDR_DQ13 2
56_4P2R_0402_5% RP92 4 3
4 3
56_4P2R_0402_5% RP66 1 DDR_DQ63 2 DDR_DQ59
DDR_DQ14 1 DDR_DQ10 2
56_4P2R_0402_5% RP107 4 3
4 3
56_4P2R_0402_5% RP100 1 DDR_DQ36 2 DDR_DQ32
56_4P2R_0402_5%
2
RP96
DDR_DQ3 DDR_DQ2
1 RP67 2
DDR_DQ7 DDR_DQ8
56_4P2R_0402_5% RP86 DDR_DQ11 1 4 DDR_DQ15 2 3
56_4P2R_0402_5% RP75 4 1 DDR_DQ33 3 2 DDR_DQ37
DDR_DQ20 1 DDR_DQ16 2
56_4P2R_0402_5% RP106 4 3
56_4P2R_0402_5% RP99 4 1 DDR_DQS4 3 2 DDR_DQ38
DDR_DQ17 1 DDR_DQ21 2
56_4P2R_0402_5% RP85 4 3
4 3
56_4P2R_0402_5% RP98 4 1 DDR_DQ35 3 2 DDR_DQ44
56_4P2R_0402_5% RP84 DDR_DQ19 1 4 DDR_DQ22 2 3
56_4P2R_0402_5% RP73 4 1 DDR_DQ40 3 2 DDR_DQ45
56_4P2R_0402_5% RP104 4 3
4 3
56_4P2R_0402_5% RP97 4 1 DDR_DQ43 3 2 DDR_DQ42
56_4P2R_0402_5% RP83 4 3
56_4P2R_0402_5% RP71 4 1 DDR_DQ47 3 2 DDR_DQ46
DDR_DQ29 1 DDR_DQS3 2
56_4P2R_0402_5%
DDR_DQ48 DDR_DQ49
DDR_DQ5 DDR_DQ1 DDR_DQS0 DDR_DQ2 DDR_DQ6 DDR_DQ8 DDR_DQ9 DDR_DQS1 DDR_DQ14 DDR_DQ15
56_4P2R_0402_5% RP53 1 DDR_DQ50 2 DDR_DQ55
<9> DDR_CLK4 <9> DDR_CLK4#
56_4P2R_0402_5% R174 56_0402_5% 1 2 1 2 R168 56_0402_5%
DDR_DM0 DDR_DM1
DDR_DQ20 DDR_DQ16 DDR_DQS2 DDR_DQ18
R173 1 1 R175
56_0402_5% 2 2 56_0402_5%
DDR_DM2 DDR_DM3
R179 1 1 R180
56_0402_5% 2 2 56_0402_5%
DDR_DM4 DDR_DM5
R177 1 1 R181
56_0402_5% 2 2 56_0402_5%
DDR_DM6 DDR_DM7
DDR_DQ22 DDR_DQ24 DDR_DQ28 DDR_DQS3 DDR_DQ26 DDR_DQ30
<9> DDR_CLK3 <9> DDR_CLK3# <9>
DDR_CKE3
DDR_CKE3
DDR_SMA12 DDR_SMA9 DDR _DQS[0..7]
DDR_SMA7 DDR_SMMAB5 DDR_SMA3 DDR_SMMAB1
DDR_DQS[0..7] <12>
DDR _DQ[0..63]
DDR_DQ[0..63] <12>
DDR_SMA[0..12]
DDR_SMA10 DDR_SBS0 DDR_SWE# DDR_SCS#2
DDR_SMA[0..12] <9,12>
D DR_DM[0..7]
<9,12> DDR_SBS0 <9,12> DDR_SWE# <9> DDR_SCS#2
DDR_DM[0..7] <12>
DDR_DQ33 DDR_DQ36
56_4P2R_0402_5% RP72 1 DDR_DQ41 2 DDR_DQS5
56_4P2R_0402_5% RP91 DDR_DQ28 1 4 DDR_DQ25 2 3 3
4 3
1 2
56_4P2R_0402_5% RP74 1 DDR_DQ34 2 DDR_DQ39
56_4P2R_0402_5% RP105 DDR_DQ18 1 4 DDR_DQS2 2 3
DDR_DQ23 1 DDR_DQ24 2
4 3
DDR_DQS4 DDR_DQ34
<9> DDR_SMAB1 <9> DDR_SMAB2 <9> DDR_SMAB4
DDR_SMAB1
2 R178
DDR_SMMAB1 1 10_0402_5%
DDR_SMAB2
2 R171
DDR_SMMAB2 1 10_0402_5%
DDR_SMAB4
2 R176
DDR_SMMAB4 1 10_0402_5%
DDR_SMAB5
2 R170
DDR_SMMAB5 1 10_0402_5%
DDR_DQ38 DDR_DQ40 DDR_DQ44 DDR_DQS5 DDR_DQ42 DDR_DQ46
56_4P2R_0402_5% <9> DDR_SMAB5
Layout note
DDR_DQ48 DDR_DQ49
Place these resistor closely DIMM1, all trace length<=800mil
DDR_DQS6 DDR_DQ54 DDR_DQ55 DDR_DQ60 DDR_DQ56 DDR_DQS7 DDR_DQ63 DDR_DQ58
PAD1
PAD2 1
PAD3 1
PAD4 1
<12,15,18,26> DIMM_SMDATA <12,15,18,26> DIMM_SMCLK
1
EMI Clip PAD for Memory Door PAD-2.5X3
PAD-2.5X3
PAD-2.5X3
+3VS
PAD-2.5X3
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 CK2# VDD CKE1 DU/A13 A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 WE# S0# DU VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDD_SPD VDD_ID
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU/RESET# VSS VSS VDD VDD CKE0 DU/BA2 A11 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# S1# DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU
1
DDR_DQ0 DDR_DQ4
2
DDR_DM0 DDR_DQ7
C488 0.1U_0402_16V4Z
DDR_DQ3 DDR_DQ12
+1.25VS
DDR_DQ13 DDR_DM1
1
DDR_DQ10 DDR_DQ11
DDR_DQ17 DDR_DQ21 DDR_DM2 DDR_DQ19 DDR_DQ23 DDR_DQ29 DDR_DQ25 DDR_DM3 DDR_DQ27 DDR_DQ31
DDR_CKE2
DDR_CKE2 <9>
DDR_SMA11 DDR_SMA8 DDR_SMA6 DDR_SMMAB4 DDR_SMMAB2 DDR_SMA0 DDR_SBS1 DDR_SRAS# DDR_SCAS# DDR_SCS#3
DDR_SBS1 <9,12> DDR_SRAS# <9,12> DDR_SCAS# <9,12> DDR_SCS#3 <9>
DDR_DQ32 DDR_DQ37
PAD12
PAD13
DDR_DQ35 DDR_DQ45
1
PAD17
PAD-2.5X3
PAD-2.5X3
56_4P2R_0402_5% 1 DDR_SMA11 2 DDR_SMA9
RP81 4 3
56_4P2R_0402_5% 1 DDR_SMA7 2 DDR_SMA8
RP78 4 3
56_4P2R_0402_5% 1 DDR_SMA6 2 DDR_SMA3
RP77 4 3
56_4P2R_0402_5% 1 DDR_SMA10 2 DDR_SMA0
1 R323 1 R182
2 DDR_SMA1 33_0402_5% 2 DDR_SMA2 33_0402_5%
RP102 4 3
33_4P2R_0402_5% 1 DDR_SMAB1 2 DDR_SMAB2
RP55 4 3
33_4P2R_0402_5% 1 DDR_SMA4 2 DDR_SMA5
RP54 4 3
33_4P2R_0402_5% 1 DDR_SMAB4 2 DDR_SMAB5
RP80 4 3
56_4P2R_0402_5% 1 DDR_SWE# 2 DDR_SBS0
RP76 4 3
56_4P2R_0402_5% 1 DDR_SRAS# 2 DDR_SCAS#
1 R358
2 DDR_SBS1 56_0402_5%
2
3
DDR_DQ43 DDR_DQ47 DDR_CLK5# <9> DDR_CLK5 <9> +1.25VS
DDR_DQ52 DDR_DQ53 DDR_DM6 DDR_DQ50 DDR_CKE3 1 DDR_CKE2 2
DDR_DQ51 DDR_DQ61
RP79 4 3
56_4P2R_0402_5% DDR_DQ57 DDR_DM7
RP101 DDR_SCS#2 1 DDR_SCS#3 2
DDR_DQ62 DDR_DQ59
4 3
56_4P2R_0402_5% +3VS
Layout note Place these resistor close by DIMM1, all trace length Max=0.8"
DIMM1
1 1
RP48 4 3
DDR_DQ41 DDR_DM5
PAD14 PAD16
1
2 DDR_SMA12 56_0402_5%
DDR_DM4 DDR_DQ39
JAE MM50-200B1-1 200P_Normal
4
1 R128
4
1
PAD-2.5X3 PAD-2.5X3
PAD-2.5X3
PAD8
PAD9
Dell-Compal Confidential PAD5
PAD6 1
PAD-2.5X3
PAD7 1
1
PAD-2.5X3
PAD-2.5X3
A
1 PAD-2.5X3
PAD10
PAD11
1 PAD-2.5X3
1 PAD-2.5X3
B
Compal Electronics, Inc. Title
1 PAD-2.5X3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
13
of
47
A
B
C
D
Layout note :
Layout note :
Di stribute as close as possible to DDR-SODIMM0.
Di stribute as close as possible to DDR-SODIMM1.
+2.5V
+2.5V
1 1 1
+
E
1 C135 150U_D2_6.3VM
2
1 C418 0.1U_0402_10V6K
2
1 C419 0.1U_0402_10V6K
2
1 C415 0.1U_0402_10V6K
2
1 C420 0.1U_0402_10V6K
2
1 C423 0.1U_0402_10V6K
2
1 C422 0.1U_0402_10V6K
2
1 C421 0.1U_0402_10V6K
2
+ C414 0.1U_0402_10V6K
1 C170 150U_D2_6.3VM
2
1 C194 0.1U_0402_10V6K
2
1 C185 0.1U_0402_10V6K
2
1 C183 0.1U_0402_10V6K
2
1 C189 0.1U_0402_10V6K
2
1 C184 0.1U_0402_10V6K
2
1 C182 0.1U_0402_10V6K
2
1 C186 0.1U_0402_10V6K
2
C190 0.1U_0402_10V6K
1
2
2
1
2
1 C164 0.1U_0402_10V6K
2
1 C167 0.1U_0402_10V6K
2
1 C166 0.1U_0402_10V6K
2
1 C162 0.1U_0402_10V6K
2
1 C160 0.1U_0402_10V6K
2
1 C157 0.1U_0402_10V6K
2
1 C158 0.1U_0402_10V6K
2
1 C168 0.1U_0402_10V6K
2
1 C169 0.1U_0402_10V6K
2
1 C177 0.1U_0402_10V6K
2
1 C172 0.1U_0402_10V6K
2
1 C173 0.1U_0402_10V6K
2
1 C179 0.1U_0402_10V6K
2
1 C175 0.1U_0402_10V6K
2
1 C176 0.1U_0402_10V6K
2
1 C181 0.1U_0402_10V6K
2
1 C180 0.1U_0402_10V6K
2
C187 0.1U_0402_10V6K
Layout note : Place one cap close to every 2 pull up resistors termination to +1.25VS
2
2
+1.25VS
1
2
1 C527 0.1U_0402_10V6K
2
1 C528 0.1U_0402_10V6K
2
1 C529 0.1U_0402_10V6K
2
1 C530 0.1U_0402_10V6K
2
1 C518 0.1U_0402_10V6K
2
1 C531 0.1U_0402_10V6K
2
1 C532 0.1U_0402_10V6K
2
1 C533 0.1U_0402_10V6K
2
1 C515 0.1U_0402_10V6K
2
C534 0.1U_0402_10V6K
+1.25VS
1
2
1 C535 0.1U_0402_10V6K
2
1 C536 0.1U_0402_10V6K
2
1 C512 0.1U_0402_10V6K
2
1 C537 0.1U_0402_10V6K
2
1 C538 0.1U_0402_10V6K
2
1 C539 0.1U_0402_10V6K
2
1 C522 0.1U_0402_10V6K
2
1 C511 0.1U_0402_10V6K
2
1 C521 0.1U_0402_10V6K
2
C513 0.1U_0402_10V6K
+1.25VS
1
3
2
1 C520 0.1U_0402_10V6K
2
1 C514 0.1U_0402_10V6K
2
1 C516 0.1U_0402_10V6K
2
1 C517 0.1U_0402_10V6K
2
1 C503 0.1U_0402_10V6K
2
C519 0.1U_0402_10V6K 3
+1.25VS
1
2
1 C509 0.1U_0402_10V6K
2
1 C510 0.1U_0402_10V6K
2
1 C508 0.1U_0402_10V6K
2
1 C507 0.1U_0402_10V6K
2
1 C504 0.1U_0402_10V6K
2
1 C502 0.1U_0402_10V6K
2
1 C501 0.1U_0402_10V6K
2
1 C497 0.1U_0402_10V6K
2
1 C495 0.1U_0402_10V6K
2
C496 0.1U_0402_10V6K
+1.25VS
1
2
1 C494 0.1U_0402_10V6K
2
1 C540 0.1U_0402_10V6K
2
1 C526 0.1U_0402_10V6K
2
1 C525 0.1U_0402_10V6K
2
1 C524 0.1U_0402_10V6K
2
1 C543 0.1U_0402_10V6K
2
1 C141 0.1U_0402_10V6K
2
1 C188 0.1U_0402_10V6K
2
1 C192 0.1U_0402_10V6K
2
C506 0.1U_0402_10V6K
+1.25VS 4
1
2
1 C137 0.1U_0402_10V6K
2
1 C178 0.1U_0402_10V6K
2
1 C191 0.1U_0402_10V6K
2
1 C139 0.1U_0402_10V6K
2
4
1 C138 0.1U_0402_10V6K
2
C505 0.1U_0402_10V6K
Dell-Compal Confidential Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
14
of
47
A
B
C
D
E
F
G
H
Clock Generator +3VS
C243 4.7U_0805_10V4Z
1
1
2
2
@10P_0402_50V8K XTALIN 2
1
2 1 C272
2 <10>
H_SEL0
2 1 2@0_0402_5%
1 R213 1 R356 1 R355
<19,30> PM_SLP_S3# <19,30> PM_SLP_S1# <19> PM_STPPCI# <19,40> PM_STPCPU#
2
XTALOUT @10P_0402_50V8K
2 1K_0402_5% 2 0_0402_5% 2 @0_0402_5%
R242 1 2 10K_0402_5%
0.1U_0402_16V4Z 1
C43
2 0.1U_0402_16V4Z
2
1 C44
0.1U_0402_16V4Z 1
C59
2 0.1U_0402_16V4Z
2
1 C58
1 C61
2 0.1U_0402_16V4Z
2
2
C306 0.1U_0402_16V4Z
2
XTAL_IN
BLM21A601SPT_0805 +3VS L23 VDDA
+3V_VDD
26
1
3
2 XTAL_OUT
54 55 40
SEL0 SEL1 SEL2
25 34 53
PWR_DWN# PCI_STOP# CPU_STOP#
28
VTT_PWRGD#
43
MULT0
VSSA
27
CPUCLKT2
45
C303
1
C312 10U_1206_10V4Z
0.1U_0402_16V4Z 2
CPU_BCLK
CPU_CLKC2
44
CPU_BCLK#
CPUCLKT1
49
MCH_BCLK
2
1
1 R225
1 R226 1 R223
1
+3VS
2
14.31818MHZ_20P
R463 H_BSEL0
2 10U_1206_10V4Z
C42
X2 R24 1K_0402_5%
<6>
C264
1
1
1
+3VS
C325
0.1U_0402_16V4Z 1
C244 0.1U_0402_16V4Z U75
C310 1
1
1 8 14 19 32 37 46 50
1
1 2 L22 @KC FBM-L11-201209-221LMAT_0805
VDD_REF VDD_PCI_0 VDD_PCI_1 VDD_3V66_0 VDD_3V66_1 VDD_48MHZ VDD_CPU_0 VDD_CPU_1
+3VS
0.1U_0402_16V4Z
1
+3V_48M
L21 BLM21A601SPT_0805 1 2
+3V_CLK L26 KC FBM-L11-201209-221LMAT_0805 Width=40 mils 1 2
2 27.4_0603_1% R218 1 1 R219
CLK_CPU_BCLK <5>
2 27.4_0603_1% 2 27.4_0603_1% R216 1 1 R217
CLK_CPU_BCLK# <5>
2 27.4_0603_1% 2 27.4_0603_1% R227 1 1 R220
CLK_MCH_BCLK# <9>
2 27.4_0603_1%
CLK_CPU_ITP# <6>
49.9_0603_1% 2 2 49.9_0603_1%
CLK_MCH_BCLK <9> 49.9_0603_1% 2 2 49.9_0603_1%
C 2
1
+CPU_CORE
2
2 B E
Q25 2SC2411K_SOT23
R232 2 10K_0402_5% 1 @1K_0603_1%
1
+3VS
3
R238 220_0402_5%
2 R221
29 30
<12,13,18,26> DIMM_SMDATA <12,13,18,26> DIMM_SMCLK
33 35
R20
<10> CLK_MCH_DISPLAY
2 475_0603_1%
R230 1
2 33_0402_5%
ICH_48M
R231 1
2 33_0402_5%
MCH_DISPLAY 38
<19> CLK_ICH_14M
R236 1
2 33_0402_5%
<27> CLK_CODEC_14M
R235 1
2 33_0402_5%
1
1
2
C247 @10P_0402_50V8K 2
ICH_14M
39
56
C248 @10P_0402_50V8K
MCH_BCLK#
52
CPU_ITP
CPUCLKC0 3V66_0 3V66_1/VCH_CLK
3V66_5 3V66_4 3V66_3 3V66_2
IREF
48MHZ_USB
PCICLK_F2 PCICLK_F1 PCICLK_F0
48MHZ_DOT PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
REF
1 R224 1 R228
CPU_ITP#
1 R222
23 22 21
AGP_66M MCH_66M ICH_66M
R255 1 R254 1 R253 1
2 2 2
7 6 5
PCI_ICH
R248 1
2
PCI_DEBUG PCI_LAN PCI_PCM PCI_MINI PCI_LPC
R457 R252 R251 R250 R249
2 2 2 2 2
51
2
CLK_CPU_ITP <6> 49.9_0603_1% 2 2 49.9_0603_1%
24
18 17 16 13 12 11 10
1 1 1 1 1
33_0402_5% 33_0402_5% 33_0402_5%
CLK_AGP_66M <16> CLK_MCH_66M <10> CLK_ICH_66M <18>
33_0402_5%
C313 @10P_0402_50V8K
ICS950810CG_TSSOP56
CLK_PCI_ICH <18>
1@33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5%
1
4 9 15 20 31 36 41 47
3
42
48
CPUCLKT0 SDATA SCLK
GND_REF GND_PCI_0 GND_PCI_1 GND_3V66_0 GND_3V66_1 GND_48MHZ GND_IREF GND_CPU
<19> CLK_ICH_48M
1
CPUCLKC1
2
CLK_PCI_DEBUG <33> CLK_PCI_LAN <22> CLK_PCI_PCM <23,25> CLK_PCI_MINI <26> CLK_PCI_LPC <30> 1
3
1
2
2
C315 @10P_0402_50V8K
C314 @10P_0402_50V8K
CPU Frequency Select Table
*
SEL[2:0]
CK-408 Speed
001
100 MHZ
011
133 MHZ
4
4
Dell-Compal Confidential Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
E
F
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003 G
Sheet
15 H
of
47
A
B
C
D
E
AGP_ST[0..2]
<10> AGP_ST[0..2]
+1.5VS
B+
+12VALW
+5VS
+5VALW
+2.5V
+2.5V
+3VS
AGP_SBA[0..7]
<10> AGP_SBA[0..7]
1
AGP_AD[0..31]
<10> AGP_AD[0..31]
AGP_C/BE#[0..3]
<10> AGP_C/BE#[0..3]
2
1 C127 0.1U_0402_16V4Z
2
1 C241 0.1U_0603_50V4Z
2
1 C240 0.1U_0402_16V4Z
2
1 C369 0.1U_0402_16V4Z
2
1 C242 0.1U_0402_16V4Z
2
1 + C372 0.1U_0402_16V4Z
1 C355 150U_D2_6.3VM
2
C239 0.1U_0402_16V4Z
2 JP8
<10> AGP_ADSTB1 <10> AGP_ADSTB1# AGP_AD25 AGP_AD27 AGP_AD29 AGP_AD31 AGP_C/BE#3 EXTVGA_IN#
<30> EXTVGA_IN#
AGP_SBA7 AGP_SBA5 AGP_SBA3 AGP_SBA1 <10> AGP_RBF# <10> AGP_WBF# <31> INTVGA_IN#
INTVGA_IN#
<10> AGP_REQ# <10> AGP_GNT# <19> PID3
STP_AGP#
<27,30,33,38> SUSP# <15> CLK_AGP_66M <17>
C /R
<17>
Y/G
<17> 3
C /R Y/ G COMP/B
COMP/B
<8,19> AGP_BUSY# <17,31> M_SEN#
M_SEN# INT_VSYNC CRT_VSYNC
<10> INT_VSYNC <17> CRT_VSYNC
INT_HSYNC CR T_HSYNC
<10> INT_HSYNC <17> CRT_HSYNC
INTDDCDA 3VDDCDA
<10> INTDDCDA <17> 3VDDCDA
INTDDCCK 3VDDCCK
<10> INTDDCCK <17> 3VDDCCK +5VALW
+1.5VS
1 EXTVGA_IN# 2 R229
4
CLK_AGP_66M
DEPOP for EXT VGA
1
2
2
AGP_AD8 AGP_AD10 AGP_AD12 AGP_AD14
C273 0.1U_0402_16V4Z
AGP_C/BE#1 +3VS
AGP_IRDY# <10> AGP_DEVSEL# <10> AGP_PIPE# <10>
R166 2
AGP_AD16 AGP_AD18 AGP_AD20 AGP_AD22
1
@0_0402_5%
AGP_AD24 AGP_AD26 AGP_AD28 AGP_AD30
STP_AGP#
4
IN1
1
IN2
2
O
U36 SN74AHC1G08HDCK_TSSOP5
SUS_STAT# <19,30> 2
PM_C3_STAT# <19> PIRQE#
<18>
AGP_SBSTB <10> AGP_SBSTB# <10> AGP_SBA6 AGP_SBA4 AGP_SBA2 AGP_SBA0
AGP_RST#
AGP_ST0 AGP_ST1 AGP_ST2
1 R237
2 2@0_0402_5% INTCRT_B CRT_B INTCRT_G CRT_G
INTCRT_B <10> CRT_B <17>
2 @0_0402_5%
V_PRST# <23,24,25>
1 R282
2 0_0402_5%
PCIRST#
<6,10,18,22,23,25,26,30,33>
+3VALW
DEPOP for INT VGA
INTCRT_G <10> CRT_G <17>
INTCRT_R CRT_R
1 R290
BKOFF# <30> ENABKL <31> PID0 <19> PID1 <19> SMB_EC_DA1 <30,31,34> SMB_EC_CK1 <30,31,34> PID2 <19> AGP_NBREF +AGPREF POP for EXT VGA
<30>
INTCRT_R <10> CRT_R <17>
1
G_RST#
2
<6,10,18,22,23,25,26,30,33> PCIRST#
A
3
O B
V_PRST#
3
U33A SN74LVC32APWLE_TSSOP14
+3V +3VS
B+
Daughter Card Present Table +12VALW
DOCKED EXTVGA_IN# INTVGA_IN# (Int. Graphy)
Terminator on VGA BD
2 R239 1K_0603_1%
POP for INT VGA
(Ext. Graphy) FOXCONN_QT00180A-5120C
R243 1 2 1@0_0402_5%
1 100K_0402_5%
1
AGP_AD0 AGP_AD2 AGP_AD4 AGP_AD6
Place this cap near AGP
R240 1K_0603_1%
AGP_NBREF
14
2
AGP_AD17 AGP_AD19 AGP_AD21 AGP_AD23 AGP_C/BE#2
+AGPREF
+3VALW AGP_ADSTB0 <10> AGP_ADSTB0# <10>
P
<10> AGP_FRAME# <10> AGP_PAR <10> AGP_TRDY# <10> AGP_STOP#
1
+1.5VS
+5VS
G
AGP_AD9 AGP_AD11 AGP_AD13 AGP_AD15
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180
7
AGP_AD1 AGP_AD3 AGP_AD5 AGP_AD7
GND 4 6 8 10 12 14 16 18 20 GND 24 26 28 30 32 34 36 38 40 GND 44 46 48 50 52 54 56 58 60 GND 64 66 68 70 72 74 76 78 80 GND 84 86 88 90 92 94 96 98 GND 102 104 106 108 110 112 114 116 118 GND 122 124 126 128 130 132 134 136 138 GND 142 144 146 148 150 152 154 156 158 GND 162 164 166 168 170 172 174 176 178 GND
5
AGP_RST# AGP_C/BE#0
on VGA BD
GND 3 5 7 9 11 13 15 17 19 GND 23 25 27 29 31 33 35 37 39 GND 43 45 47 49 51 53 55 57 59 GND 63 65 67 69 71 73 75 77 79 GND 83 85 87 89 91 93 95 97 GND 101 103 105 107 109 111 113 115 117 GND 121 123 125 127 129 131 133 135 137 GND 141 143 145 147 149 151 153 155 157 GND 161 163 165 167 169 171 173 175 177 GND
P
AGP BUS Pullup
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179
G
+2.5V
3
1
NON DOCKED
LOW
HIGH
LOW
HIGH
4
Dell-Compal Confidential Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
16
of
47
5
4
3
2
1
C236 33P_0402_50V8J 1 2
C /R
C /R
1 2 L18 FLM1608081R8K_0603
1
<16>
D
2
1
R203 75_0603_1% 2
2
C227 100P_0402_50V8J
D
C221 270P_0603_50V8J
1
C233 33P_0402_50V8J 1 2
JP3 3 6 7 5 2 4 1 8 9
SVIDEO_C SVIDEO_CVBS
1 2 L19 FLM1608081R8K_0603 2
SVIDEO_Y
1
C222 270P_0603_50V8J
1
SUYIN_35138S-07T1-01
1
R205 75_0603_1% C
2
2
1
1
1 2 L20 FLM1608081R8K_0603
D5 @DAN217_SOT23
2
Y/ G
2
Y/G
1
<16>
D4 @DAN217_SOT23
3
D19 @DAN217_SOT23
C228 33P_0402_50V8J 1 2
1
2
2
C225 100P_0402_50V8J
3
R204 75_0603_1%
2
COMP/B
3
COMP/B
1
<16>
+3VS
2
C226 100P_0402_50V8J
C220 270P_0603_50V8J
1
C
CRTVCC CRTVCC
1
1 R4 0_0402_5%
R202 2.7K_0402_5%
R3
2 G
2
CRTVCC
2
2
2
2.7K_0402_5% R201 2K_0402_5%
1
1 R5 2K_0402_5%
2
2
C14 0.1U_0402_16V4Z
+3VS
1
+3VS 1
1
CRT_G
<16>
CRT_B
R7 1K_0402_5% 1 2
OE#
2
2
1
5 P CR T_HSYNC
A
4
1
2
2
C2 3.3P_0603_50V8J 2
3
A
2
3
A
2
C6 0.1U_0402_16V4Z
3
2
D
2 G
6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
1 C214 3.3P_0603_50V8J
2
C1 3.3P_0603_50V8J
B
CRT Connector
4
1
1 C217 27P_0402_50V8J
2
1 C218 27P_0402_50V8J
1 C8
1 C7
2
2
1 C5
2
2
C224 100P_0402_50V8J
100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J
R460 Y
G
2
OE#
P
1
5
1
CRT_VSYNC
3
2 1
1 2 L17 1 FBM-11-160808-121-T_0603
CRTVCC
SN74AHCT1G125GW_SOT353-5
<16> CRT_VSYNC
3VDDCCK <16>
1 2 L16 FBM-11-160808-121-T_0603
R459 33_0402_5%
U13
3
R2 75_0603_1%
Q23 2N7002_SOT23
FOX_DZ11A91-L8 Y
G
<16> CRT_HSYNC
R195 2
R1 75_0603_1%
1 2
2
CRTR 1 2 L2 FBM-10-201209-260-T_0805 CRTG 1 2 L15 FBM-10-201209-260-T_0805 CRTB 75_0603_1% 1 2 L1 FBM-10-201209-260-T_0805 1
CRT_B
Q24 SI2303DS_SOT23 SUSP
2
CRT_G
CRTVCC
<7,33>
2
DDC_MONID0
3VDDCDA <16>
JP1
1
<16>
CRT_R
1
CRT_R
1
+5VS
<16>
3VDDCCK
3
+3VS
C4 @3.3P_0603_50V8J
2
B
3VDDCDA
3
Q14 2N7002_SOT23 1
1 C219
3
1
2
1 C3 @3.3P_0603_50V8J
2
S
@3.3P_0603_50V8J
S
1
C15 0.1U_0402_16V4Z
D
1
DAN217_SOT23 D3
1
M_SEN#
M_SEN#
DAN217_SOT23 D18
1
DAN217_SOT23 D1 <16,31>
2
33_0402_5% A
U4 SN74AHCT1G125GW_SOT353-5
Dell-Compal Confidential Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5
4
3
2
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet 1
17
of
47
A
B
C
D
U55A AD [0..31]
1
R319 2
+CPU_CORE
1
H_FERR#
62_0402_5%
Place closely pin P5
1
CLK_PCI_ICH
2
R348 22_0402_5%
1 C480 10P_0402_50V8K
2
Place closely pin T21 1
CLK_ICH_66M R321 22_0402_5%
C/BE#0 C/BE#1 C/BE#2 C/BE#3 REQ#0 REQ#1 REQ#2
2
<22> <26> <23,25> 1
C395 15P_0402_50V8J
<22> <26> <23,25>
2
<15> CLK_PCI_ICH
PCI Pullups RP5 10 9 8 7 6
PIRQA# PIRQB# REQ#4
+3VS
<30> EC_WAKEUP#
8.2K_10P8R_1206_5% <21> <21>
RP3 10 9 8 7 6
B1 A2 B3 C7 B6
REQ#0 REQ#1 REQ#2 REQ#3 REQ#4
C1 E6 A7 B7 D6 CLK_PCI_ICH
P5
PCI_PLOCK#
F1 M3 L5 G1 L4 M2 W2 U5 K5 F3 F2
ICH_PCIRST#
PIDERST# SIDERST#
REQA# REQB# PIDERST# SIDERST#
B5 A6 E8 C5
A20GATE A20M# DPSLP# FERR# IGNNE# INIT# INTR NMI CPU_PWRGOOD RCIN# SLP# SMI# STPCLK#
CPU I/F
SM_INTRUDER# SMLINK0 R164 1 SMLINK1 R172 1 SMB_CLK SMB_DATA AC IN
Y22 AB23 U23 AA21 W21 V22 AB22 V21 Y23 U22 U21 W23 V23
GATEA20 R104 2
1 68_0402_5%
R110 2
1 68_0402_5%
R105 2 R91 2 R103 2
1 68_0402_5% 1 68_0402_5% 1 68_0402_5%
R112 2 R102 2 R101 2
1 68_0402_5% 1 68_0402_5% 1 68_0402_5%
1
ACIN
<30,34,36>
GATEA20 <30> H_A20M# <6> H_DPSLP# <6> H_FERR# <6> H_IGNNE# <6> H_INIT# <6> H_INTR <6> H_NMI <6> H_PWRGD <6> KBRST# <30> H_SLP# <6> H_SMI# <6> H_STPCLK# <6>
+3VS DIMM_SMCLK DIMM_SMDATA
HUB I/F
HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 HI10 HI11
GNT#0 GNT#1 GNT#2 GNT#3 GNT#4 PCICLK FRAME# DEVSEL# IRDY# PAR PERR# LOCK# PME# PCIRST# SERR# STOP# TRDY# REQA#/GPI0 REQB#/GPI1/REQ5# GNTA#/GPO16 GNTB#/GPO17/GNT5#
CLK66
T21 P21 N20
APICCLK APICD0 APICD1 PIRQA# PIRQB# PIRQC# PIRQD# PIRQE#/GPI2 PIRQF#/GPI3 PIRQG#/GPI4 PIRQH#/GPI5 IRQ14 IRQ15 SERIRQ EE_CS EE_IN EE_OUT EE_SHCLK
EEPROM I/F
HI[0..10] HI[0..10] HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 H I10 1 2 R99 62_0402_5% CLK_ICH_66M CLK_ICH_66M <15>
HUB_RCOMP_ICH 1 HUB_VREF R87 HUB_VSWING
J19 H19 K20 D5 C2 B4 A3 C8 D7 C3 C4 AC13 AA19 J22
APICCLK APICD0 APICD1 PIRQA# PIRQB# PIRQC# PIRQD# PIRQE# GPI3 GPI4 GPI5 IRQ14 IRQ15 SIRQ
2 68_0603_1%
SMB_DATA
<23,25> <22> <26> <26> <16>
IRQ14 IRQ15 SIRQ
<21> <21> <23,25,30>
2 8.2K_0402_5% 2 8.2K_0402_5% 2
IRQ14
1 R143 1 R123
2 8.2K_0402_5% 2 8.2K_0402_5%
KBRST#
1 R95 1 R94
2 10K_0402_5% 2 10K_0402_5%
GPI4 GPI3 PIRQE# GPI5
1 2 3 4
IRQ15
+1.5VS
GATEA20
RP4 8 7 6 5 8.2K_8P4R_1206_5%
R156 1
2
3
+3VALW @1K_0402_5%
LAN
LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 I/F LAN_TXD1 LAN_TXD2 LAN_CLK LAN_RSTSYNC LAN_RST#
A10 A9 A11 B10 C10 A12 C11 B11 Y5
1 2 R165 8.2K_0402_5% SMLINK1 1 2 R169 8.2K_0402_5% AC IN 1 2 R161 @10K_0402_5%
R159 1
2
10K_0402_5%
RP2 REQ#0 REQ#1 REQ#2 REQ#3
APICCLK APICD0 APICD1
ICH4
2
8 7 6 5
R89 10K_0402_5%
8.2K_8P4R_1206_5% REQB# 1 2 R158 8.2K_0402_5% PIDERST# (Strap) 2 @8.2K_0402_5% 2
R97 10K_0402_5%
G
1
SMB_CLK
D
2 G
DIMM_SMCLK 3 S
<12,13,15,26> DIMM_SMCLK
R88 0_0402_5% 1
+3VS 1 R153
1 R353 1 R352
+3VS
HUB_VREF <9,11> HUB_VSWING <9,11>
PIRQA# PIRQB# PIRQC# PIRQD# PIRQE#
2 8.2K_0402_5% 2 8.2K_0402_5%
+3VALW SMB_CLK
HUB_PSTRB <9> HUB_PSTRB# <9>
R23 M23 R22
D10 D11 A8 C12
<9>
1 R163 1 R162
SMLINK0
+3VS PIRQC# PIRQD# SIRQ PCI_PLOCK#
+3VS
L19 L20 M19 M21 P19 R19 T20 R20 P23 L22 N22 K21
HI_STB HI_STB# HICOMP HUB_VREF HUB_VSWING
8.2K_10P8R_1206_5%
1 2 3 4
SM_INTRUDER# <32>
2 @0_0402_5% 2 @0_0402_5%
2
+3VS
1 2 3 4 5
REQ#0 REQ#1 REQ#2 REQ#3 REQ#4
<22,23,25,26> PCI_SERR# <22,23,25,26> PCI_STOP# <22,23,25,26,33> PCI_TRDY#
3
PCI_IR DY# PC I_TRDY# PCI_DEVSEL# PCI_FRAME#
C/BE#0 C/BE#1 C/BE#2 C/BE#3
SM I/F
W6 AC3 AB1 AC4 AB4 AA5
1
+3VS
1 2 3 4 5
J2 K4 M4 N4
INTRUDER# SMLINK0 SMLINK1 SMB_CLK SMB_DATA SMB_ALERT#/GPI11
2
PCI_PERR# REQA# PCI_STOP# PCI_SERR#
C/BE#0 C/BE#1 C/BE#2 C/BE#3
GNT#0 GNT#1 GNT#2
<22,23,25,26,33> PCI_FRAME# <22,23,25,26> PCI_DEVSEL# <22,23,25,26> PCI_IRDY# <22,23,25,26> PCI_PAR <22,23,25,26> PCI_PERR#
ICH4 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
1
2
<22,23,25,26,33> <22,23,25,26,33> <22,23,25,26,33> <22,23,25,26,33>
H5 J3 H3 K1 G5 J4 H4 J5 K2 G2 L1 G4 L2 H2 L3 F5 F4 N1 E5 N2 E3 N3 E4 M5 E2 P1 E1 P2 D3 R1 D2 P4
Interrupt I/F
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
PCI I/F
<22,23,24,25,26,33> AD[0..31]
+3VS
5 2
3
DIMM_SMDATA
4
DIMM_SMDATA <12,13,15,26>
P
Q27 2N7002_SOT23
IN1
O
4
PCIRST#
Dell-Compal Confidential
<6,10,16,22,23,25,26,30,33>
IN2
G
1
3
ICH_PCIRST#
SMB_DATA 1
S
Q28 2N7002_SOT23
D
4
Compal Electronics, Inc.
U9 SN74AHC1G08HDCK_TSSOP5
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date:
A
B
C
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet D
18
of
47
A
B
C
D
Place close to pin B8
+3VALW
+3VS
R336 @10_0402_5%
1 R90
PM_STPCPU# 2 1K_0402_5%
1 R78
PM_STPPCI# 2 1K_0402_5%
<8,16> AGP_BUSY# <6> SYSRST# <30> VLBA# <16> PM_C3_STAT#
ICLKRUN#
<40> PM_DPRSLPVR <30> PWRBTN# <10,30,32> PM_PWROK <30> EC_SWI# <30> RSMRST# <15,30> PM_SLP_S1# <15,30> PM_SLP_S3# <30> PM_SLP_S4# <30> PM_SLP_S5# 2 1 R84 2 1 @0_0402_5% R81 @0_0402_5%
<15,40> PM_STPCPU# <15> PM_STPPCI#
<16,30> SUS_STAT#
R391 @0_0402_5% 2 1
ICH_THRM#
2
IAC_BITCLK 2 R160 IAC_SDATA_IN0 IAC_SDATA_IN1
1 B8 33_0402_5% C13 D13 A13 B13 ICH_AC_SDOUT D9 ICH_AC_SYNC C9
<27,29> IAC_BITCLK <27,29> IAC_RST# <27> IAC_SDATA_IN0 <29> IAC_SDATA_IN1 ICH_THRM#
1
J21 Y20 V19
R96
R392 <30> EC_THRM#
RTCCLK
PM_CPUPERF# V_GATE 2 1 33_0402_5%
<6> PM_CPUPERF# <30,40> VGATE
<6,31> PROCHOT#
EC_SWI#
ICH4 AGPBUSY#/GPI6 SYSRST# BATLOW# C3_STAT#/GPO21 CLKRUN#/GPIO24 DPRSLPVR PWRBTN# PWROK RI# RSMRST# SLP_S1#/GPO19 SLP_S3# SLP_S4# SLP_S5# STP_CPU#/GPO20 STP_PCI#/GPO18 SUS_CLK SUS_STAT#/LPCPD# THRM#
SSMUXSEL/GPO23 CPUPERF#/GPO22 VGATE/VRMPWRGD
GPIO
2 RTCCLK @100K_0402_5%
1 R347
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
LAD0 LAD1 LAD2 LAD3
T2 R4 T4 U2 U3 U4 T5
LFRAME#
<30> LFRAME#
<32> <32>
USBP0+ USBP0-
<32> <32>
USBP2+ USBP2-
C20 D20 A21 B21 C18 D18 A19 B19 C16 D16 A17 B17
+3VS
1
2 100K_0402_5% PID0
<32>
OVCUR#0
R83
1
2 100K_0402_5% PID1
<32>
OVCUR#2
R80
1
2 100K_0402_5% PID2
R77
1
2 100K_0402_5% PID3
OVCUR#0 OVCUR#1 OVCUR#2 OVCUR#3 OVCUR#4 OVCUR#5
B15 C14 A15 B14 A14 D14
USB_RBIAS
A23 B23
EC_SMI# <30> SCI# <30> LID_OUT# <30> EC_FLASH# <30>
2
IST
AC97 I/F
PDA0 PDA1 PDA2 PDCS1# PDCS3#
AA13 AB13 W13 Y13 AB14
PDA0 PDA1 PDA2 PDCS1# PDCS3#
PDDREQ PDDACK# PDIOR# PDIOW# PIORDY
AA11 Y12 AC12 W12 AB12
PDDREQ PDDACK# PDIOR# PDIOW# PDIORDY
PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
AB11 AC11 Y10 AA10 AA7 AB8 Y8 AA8 AB9 Y9 AC9 W9 AB10 W10 W11 Y11
PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
AA20 AC20 AC21 AB21 AC22
SDA0 SDA1 SDA2 SDCS1# SDCS3#
AB18 AB19 Y18 AA18 AC19
SDDREQ SDDACK# SDIOR# SDIOW# SDIORDY
W17 AB17 W16 AC16 W15 AB15 W14 AA14 Y14 AC15 AA15 Y15 AB16 Y16 AA17 Y17
SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
IDE I/F
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_DRQ#0 LPC_DRQ#1 LPC_FRAME#
LPC I/F
SDA0 SDA1 SDA2 SDCS1# SDCS3# SDDREQ SDDACK# SDIOR# SDIOW# SIORDY SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
USB I/F
OC#0 OC#1 OC#2 OC#3 OC#4 OC#5
PDA0 PDA1 PDA2 PDCS1# PDCS3#
<21> <21> <21> <21> <21>
PDDREQ PDDACK# PDIOR# PDIOW# PDIORDY
<21> <21> <21> <21> <21>
CLK_ICH_14M R93 @10_0402_5%
1
2
CLK_ICH_48M 2
R92 @10_0402_5%
1
SDA0 SDA1 SDA2 SDCS1# SDCS3#
<21> <21> <21> <21> <21>
SDDREQ SDDACK# SDIOR# SDIOW# SDIORDY
<21> <21> <21> <21> <21>
2 PDD [0..15]
PDD[0..15] <21>
SDD [0..15]
SDD[0..15] <21>
3
+RTCVCC R145 15K_0402_5% 2 1
USB_RBIAS USB_RBIAS#
1
OVCUR#1
2 8.2K_0402_5%
OVCUR#3
R130 1
2 8.2K_0402_5%
OVCUR#4
<21> SIDEPWR
R147 1
2 8.2K_0402_5%
OVCUR#5
<16> <16> <16> <16>
+3VS
<22,25,26,30> CLKRUN#
1
PID0 PID1 PID2 PID3
R346 10K_0402_5% 2
CLK14 CLK48 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43
RTCRST#
CLOCK
VBIAS RTCX1
GPIO
RTCX2 SPKR
MISC THRMTRIP#
J23 F19
CLK_ICH_14M <15> CLK_ICH_48M <15>
W7
RTC_RST#
Y6
VBIAS
AC7
RTCX1
2
1 J1 JOPEN
2
1
AC6
2
R326 1K_0402_5% 1
RTCX2
H23
ICH_SPKR <28>
W20 H_THERMTRIP#
H_THERMTRIP# <6> C450 12P_0402_50V8J
D46 @RB751V_SOD323 ICLKRUN# 1
2 1 10M_0603_5% X3 32.768KHZ_12.5P 1 2 R331 10M_0603_5% 1 1
2
2
C156 1U_0603_10V4Z
R_VBIAS1
C163 0.047U_0402_16V4Z
R329
ICH4
CLKRUN#
2
2
2
2 8.2K_0402_5%
R142 1
1
R144 1
J20 G22 F20 G20 F21 H20 F23 H22 G23 H21 F22 E23
C123 @10P_0402_50V8K
2 R324
2 R154 1K_0402_5%
1 @22M_0603_5%
R330 @2.4M_0603_1%
C448 12P_0402_50V8J 1
R86 22.6_0603_1%
+3VALW
C124 @10P_0402_50V8K
Place close to pin F19
2
3
R82
EC_SMI# SCI# LID_OUT#
C460 @10P_0402_50V8K
Place close to pin J23
AC_BITCLK AC_RST# AC_SDATAIN0 AC_SDATAIN1 AC_SDATAIN2 AC_SDATAOUT AC_SYNC
USBP0+ USBP0USBP1+ USBP1USBP2+ USBP2USBP3+ USBP3USBP4+ USBP4USBP5+ USBP5-
GPI7 GPI8 GPI12 GPO13 GPIO25 GPIO27 GPIO28
PM
0_0402_5% <30> <30> <30> <30>
1
1 R3 V4 V5 W3 V2 W1 W4
1
ICH_AC_SDOUT 2 @8.2K_0402_5%
R2 Y3 AB2 T3 AC2 V20 AA1 AB6 Y1 AA6 W18 Y4 Y2 AA2 W19 Y21 AA4 AB3 V1
2
1 R150
AGP_BUSY# SYSRST# VLBA#
1
ICH_SPKR 2 @1K_0402_5%
2
1 R98
2
2
U55B
1
2
1
1
IAC_BITCLK R79 10K_0402_5%
4
4
1
1 R335 1 R325 1
2
2
<27,29> IAC_SYNC <27,29> IAC_SDATAO C457 @22P_0402_50V8J
ICH_AC_SYNC 2 33_0402_5% ICH_AC_SDOUT 2 33_0402_5%
Dell-Compal Confidential
C452 @22P_0402_50V8J
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date:
A
B
C
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet D
19
of
47
A
B
C
D
E
F
G
H
U55C
E11 F10 F15 F16 F17 F18 K14 V7 V8 V9
+3VALW
VCC1.5_0 VCC1.5_1 VCC1.5_2 VCC1.5_3 VCC1.5_4 VCC1.5_5 VCC1.5_6 VCC1.5_7
K10 K12 K18 K22 P10 T18 U19 V14
+1.5VS
VCCSUS1.5_0 VCCSUS1.5_1 VCCSUS1.5_2 VCCSUS1.5_3 VCCSUS1.5_4 VCCSUS1.5_5 VCCSUS1.5_6 VCCSUS1.5_7
E12 E13 E20 F14 G18 R6 T6 U6
+1.5VALW
POWER
VCC5REF1 VCC5REF2 VCC5REFSUS1 VCCHI_0 VCCHI_1 VCCHI_2 VCCHI_3 VCC_CPU_IO_0 VCC_CPU_IO_1 VCC_CPU_IO_2 VCCPLL VCCRTC
2 4.7U_0805_10V4Z
2
VCCLAN1.5_0 VCCLAN1.5_1
2
1 C441 0.1U_0402_16V4Z
2
1 C9 0.1U_0402_16V4Z
2
1 C416 0.1U_0402_16V4Z
2
1 C466 0.1U_0402_16V4Z
C424 0.1U_0402_16V4Z
2
1 C463 0.1U_0402_16V4Z
2
1 C449 0.1U_0402_16V4Z
2
1 C430 0.1U_0402_16V4Z
2
1 C397 0.1U_0402_16V4Z
2
1 C469 0.1U_0402_16V4Z
2
1 C473 0.1U_0402_16V4Z
2
1 C472 0.1U_0402_16V4Z
C443 0.1U_0402_16V4Z
2
+3VALW
1
2
1 C433 4.7U_0805_10V4Z
1
2
2
1 C434 0.1U_0402_16V4Z
1 C447 0.1U_0402_16V4Z
2
2
1 C431 0.1U_0402_16V4Z
1 C436 0.1U_0402_16V4Z
2
2
1 C451 0.1U_0402_16V4Z
2
1 C464 0.1U_0402_16V4Z
2
1 C454 0.1U_0402_16V4Z
C442 0.1U_0402_16V4Z
2
1 C396 0.1U_0402_16V4Z
2
C426 0.1U_0402_16V4Z
2
+1.5VS
1
2
1 C425 4.7U_0805_10V4Z
2
1 C427 0.1U_0402_16V4Z
2
1 C437 0.1U_0402_16V4Z
2
1 C467 0.1U_0402_16V4Z
2
1 C465 0.1U_0402_16V4Z
2
1 C446 0.1U_0402_16V4Z
2
1 C440 0.1U_0402_16V4Z
1 C445 0.1U_0402_16V4Z
2
2
C398 0.1U_0402_16V4Z
VCC5REF
VCC DECOUPLING VCC5REFSUS
L23 M14 P18 T22
+1.5VS
AA23 P14 U18
+CPU_CORE
+1.5VS
+1.5VALW
1
2
1 C417 0.1U_0402_16V4Z
2
1 C453 0.1U_0402_16V4Z
2
1 C459 4.7U_0805_10V4Z
2
1 C444 0.1U_0402_16V4Z
2
1 C429 0.1U_0402_16V4Z
2
1 C435 0.1U_0402_16V4Z
2
C439 4.7U_0805_10V4Z
+1.5VS_PLL C22 AB5
1 R85
VCCHI DECOUPLING
2 +1.5VS 0_0805_5% +RTCVCC
+3VS_ICHLAN VCCLAN3.3_0 VCCLAN3.3_1
2
1 C428 0.1U_0402_16V4Z
1
1
E7 V6 E15
2
1 C140 0.1U_0402_16V4Z
E9 F9 F6 F7
+CPU_CORE
1 2 +3VS R338 0_0805_5% +1.5VS_ICHLAN 1 R332
1
2 +1.5VS 0_0805_5%
2
+1.5VS_ICHLAN
1 C130 0.1U_0402_16V4Z
2
1 C438 0.1U_0402_16V4Z
2
1 C432 1U_0603_10V4Z
2
1 C468 0.1U_0402_16V4Z
2
1 C462 0.1U_0402_16V4Z
2
1 C455 4.7U_0805_10V4Z
2
1 C456 0.1U_0402_16V4Z
1
1 C153 0.1U_0402_10V6K
2
D23 1SS355_SOD323 1
C129 0.1U_0402_16V4Z
2
VCC5REFSUS C128 0.01U_0402_25V4Z C136 1U_0603_10V4Z
1
2
R111 1K_0603_1%
1
VCC5REF
C143 0.1U_0402_16V4Z
2
2
C475 1U_0603_10V4Z
C461 0.1U_0402_16V4Z
+5VS
D13 1SS355_SOD323
R349 1K_0603_1% 1
+1.5VS_PLL
2
+3VS 2
+3VALW +5VALW
+RTCVCC
3
+3VS_ICHLAN
1
GND
1 C146
1
1
2
2
2
VCCSUS3.3_0 VCCSUS3.3_1 VCCSUS3.3_2 VCCSUS3.3_3 VCCSUS3.3_4 VCCSUS3.3_5 VCCSUS3.3_6 VCCSUS3.3_7 VCCSUS3.3_8 VCCSUS3.3_9
1
1
3
+3VS
2
2
+3VS A5 AC17 AC8 B2 H18 H6 J1 J18 K6 M10 P12 P6 U1 V10 V16 V18
VCC3.3_0 VCC3.3_1 VCC3.3_2 VCC3.3_3 VCC3.3_4 VCC3.3_5 VCC3.3_6 VCC3.3_7 VCC3.3_8 VCC3.3_9 VCC3.3_10 VCC3.3_11 VCC3.3_12 VCC3.3_13 VCC3.3_14 VCC3.3_15
2
1
ICH4 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101
1
D22 E10 E14 E16 E17 E18 E19 E21 E22 F8 G19 G21 G3 G6 H1 J6 K11 K13 K19 K23 K3 L10 L11 L12 L13 L14 L21 M1 M11 M12 M13 M20 M22 N10 N11 N12 N13 N14 N19 N21 N23 N5 P11 P13 P20 P22 P3 R18 R21 R5 T1 T19 T23 U20 V15 V17 V3 W22 W5 W8 Y19 Y7 A16 A18 A20 A22 A4 AA12 AA16 AA22 AA3 AA9 AB20 AB7 AC1 AC10 AC14 AC18 AC23 AC5 B12 B16 B18 B20 B22 B9 C15 C17 C19 C21 C23 C6 D1 D12 D15 D17 D19 D21 D23 D4 D8 A1
C474 0.1U_0402_16V4Z
ICH4 4
4
Dell-Compal Confidential Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
E
F
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003 G
Sheet
20 H
of
47
A
B
C
Placea caps. near HDD CONN.
HDD Connector SDD [0..15]
0.1U_0402_16V4Z C386
Correct HDD pin define ,pls update layout JP6
<18> IRQ15 <19> SDA1 <19> SDA0 <19> SDCS1#
SHDD_LED# +5VSHDD
C387
2
SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
C375
2
C377
2
22U_1206_10V4Z
1 1
C643 @22U_1206_10V4Z
2
G
0.1U_0402_16V4Z
3
2
S
+5VS
+5VSHDD
+12VALW
SDIORDY 2 4.7K_0402_5%
1 R280
+3VS
3 R55 100K_0402_5%
1 Q6 SI2301DS_SOT23
2
R274 470_0402_5% SEC_CSEL1 2
SDA2 SDCS3#
<19> <19>
RSDDACK# 2 22_0402_5%
1 R289
<19> SDDACK#
+5VSHDD 1
SDIORDY RSDDACK# IRQ15
C389
1
FOX_HH99227-S1-TR
2 G Q18 2N7002_SOT23
<19> SIDEPWR SDDREQ
1
2
D
S
1
R54 150K_0603_5%
2
2
SDDREQ
SDDREQ SDIOW# SDIOR# SDIORDY
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
2
1
1
<19> <19> <19> <19>
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43
SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0
2
1 D
1U_0603_10V4Z 1
2
<18> SIDERST#
1000P_0402_50V7K
1
1
1
1
SI2301DS: P CHANNEL VGS: -4.5V, RDS: 130 mOHM VGS: -2.5V, RDS: 190mOHM Id(MAX): 2.3A VGS(MAX): +-8V
3
SDD[0..15]
E
Layout Note: +5VSHDD trace width 60 mil
+5VSHDD <19>
D
C86 0.1U_0402_16V4Z
C323 33P_0402_50V8J 2
2
+3VS
PDIORDY 2 4.7K_0402_5%
1 R370
CD-ROM Connector PDD [0..15]
<19> PDD[0..15]
<19>
RPDDACK# 2 22_0402_5%
1 R371
PDDACK#
+5VS
1 14 C195 2
1
1
PDDREQ
1
2
JP14
PIDERST#
<19> <19> <18> <19> <19> <19>
PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0
PDIOW# PDIORDY IRQ14 PDA1 PDA0 PDCS1#
PDIORDY IRQ14
PHDD_LED#
+5VS
2
PRI_CSEL
INT_CD_R <27> PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDDREQ
O I1
3 U18A 74HCT08PW_TSSOP14 3
Placea caps. near CDROM CONN. PDDREQ <19> PDIOR# <19>
+5VS +5VS
RPDDACK#
R374 100K_0402_5% 1 2
PDIAG# W=80mils
PDA2 PDCS3#
+5VS
1
<19> <19> 2
1
C567
1
C565
1000P_0402_50V7K 0.1U_0402_16V4Z 2
1
2
C204 1U_0603_10V4Z
1
2
C202
R67 100K_0402_5%
10U_1206_10V4Z
+5VS
2
C563 0.1U_0402_16V4Z
+5VS
1
SUYIN_800185MB050S106ZU
1
R185 470_0402_5%
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
I0
7
<18>
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
2
INT_CD_L
C559 33P_0402_50V8J
1
3
<27>
2 47P_0402_50V8J
P
CD_AGND <27>
47P_0402_50V8J
2 C105 0.1U_0402_16V4Z
G
2
47P_0402_50V8J
2
1
C206 1000P_0402_50V7K
2
C561 0.1U_0402_16V4Z
1
2
C205 1U_0603_10V4Z
1
2
2
1 C196
2
R74 100K_0402_5% 1
1 C197
PHDD_LED#
4
SHDD_LED#
5
I0 O I1
6
ACT_LED#
ACT_LED# <29>
U18B 74HCT08PW_TSSOP14
C203 10U_1206_10V4Z
4
4
Dell-Compal Confidential Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
21
of
47
5
4
3
2
1
+1.8VLAN +3VWOL 0.1U_0402_16V4Z 1 C96
1
C97
C94
2
10U_1206_10V4Z
1
C77
2 0.1U_0402_16V4Z
C87
2
2
1
1
C88
C74
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z 1
1
C80 0.1U_0402_16V4Z
2
C41 4.7U_0805_10V4Z
1
+1.8VLAN +3VWOL
+1.8VLAN
2
GREEN (10M)
ACTLED#
YELLOW
NC
WLAN_LINK_10_LDE
ORANGE/GREEN
D
1
1 C46
2
2
1
1
C55 10U_1206_10V4Z
2
C48 0.1U_0402_16V4Z
2
1
1
C45 0.1U_0402_16V4Z
2
C47 0.1U_0402_16V4Z
C38 0.1U_0402_16V4Z
2
+3VAUXLAN
C67 1000P_0402_50V7K
1000P_0402_50V7K
2
1 3 1
3 1 3 1 3 1
3 SPROM_CS SPROM_CLK SPROM_DOUT SPROM_DI
98 95 101 99
1
VCC NC ORG GND
C20 0.1U_0402_16V4Z 2 R452 @100K_0402_5%
R15 1
2
200_0603_5%
+3VAUXLAN
JP7 LAN_RJ45T+
1
SPROM_DOUT 1Kb
None
4Kb
XTAL_IN XTAL_OUT
SPROM_CLK
VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11
16Kb
None
3 4
LAN_RX+ LAN_RX-
None
10K Pullup
1 2
None 10K Pullup
5 6
1
1
2
2
TD+ TD-
TX+ TX-
TDC RDC
TCT RCT
RD+ RD-
RX+ RX-
12 11
LAN_RJ45T-
2
LAN_RJ45R+
3
5 8 7
2
Close to RJ45 under inch
2
1
6
8
R193 75_0603_1% C215 0.01U_0402_25V4Z
C54 4.7U_0805_10V4Z
LAN_RJ45R-
7 Pulse_H1112 C213 0.01U_0402_25V4Z
EPHY_PLLVDD
C40 27P_0402_50V8J
4
10 9
C52 1000P_0402_50V7K
R190
R192
1
PR1+ PR1PR2+ PR3+
B
PR3PR2PR4+ PR4-
FOX_JM66113-L1B1-TR R191 75_0603_1%
75_0603_1% 75_0603_1% 2
2
Place closely pin 118
1
LAN_TX+ LAN_TX-
1
LAN_DISABLE# <30>
1
JTAG_TDO JTAG_TCK JTAG_TDI JTAG_TRST_L JTAG_TMS
89 83 80 82 73 81
1
C39 2 27P_0402_50V8J
CS SK DI DO
8 7 6 5
AT93C46_SO8
90 93
PCI_CLKRUN_L
BCM4401_LQFP128
1
1
87 86 85
1
U8 1 2 3 4
1 1
R25 @10K_0402_5%
R30 @10K_0402_5%
2
R35 1K_0402_5%
2
XO
+3VAUXLAN
+3VAUXLAN
2
2
2
XI 1
Q5 DTA114YKA_SOT23
C
U2
EXT_POR_L PCI_RST_L PCI_CLK PCI_GNT_L PCI_REQ_L PCI_PME_L PCI_IDSEL
R29 200_0603_5%
10K
+3VAUXLAN
12 46 111 100 84 2 24 74 13 47 120 35
Y1 25MHZ_20P
2 S Q17 2N7002_SOT23
E
13
SPROM_CS SPROM_CLK SPROM_DOUT SPROM_DIN
47K
B
LED_YELLOW-
BOOTROM_SCL BOOTROM_SDA
2 1 200_0603_5%
D
11
VAUX_AVAIL NC8 NC9
C
R13
12
PCI_CBE3_L PCI_CBE2_L PCI_CBE1_L PCI_CBE0_L PCI_FRAME_L PCI_IRDY_L PCI_TRDY_L PCI_DEVSEL_L PCI_STOP_L PCI_PERR_L PCI_SERR_L PCI_PAR PCI_INT_L
D10 RB751V_SOD323 2 G
<26> WLAN_ACT_LED
1
NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7
104 105 103 108 102 109 110 107
(LAN_ACTIVE)
2
G_O_LED-
LAN_TX+ LAN_TXLAN_RX+ LAN_RX-
2 @10K_0402_5% 2 1.27K_0603_1%
1
LED_YELLOW+
62 61 59 60
ACTLED#
1 2 +1.8VLAN LCN0603T-R22J-S_5%_0603
Q3 DTA114YKA_SOT23
C
+3VAUXLAN
SHLD2
EPHY_TDP EPHY_TDN EPHY_RDP EPHY_RDN
10K
SHLD1
R34 1 R28 1
2
L8
EPHY_PLLVDD
47K
B
Q15 2N7002_SOT23
15
71 72 88
S
R14 2 1 200_0603_5% E
14
EPHY_VREF EPHY_RDAC EPHY_TESTMODE
D
9
64 63
+3VAUXLAN
Q4 DTA114YKA_SOT23
10
EPHY_PLLVDD EPHY_PLLGND
(LAN_100LINK)
LDE_GREEN+
69 70
C
LDE_ORANGE+
EPHY_BIAS_AVDD EPHY_BIAS_AVSS
<26> WLAN_LINK_80211A
10K +3VAUXLAN
2
D2 RB751V_SOD323 2 RB751V_SOD323G D7 1 2
+1.8VLAN
S
1
58 57
1
E
2
2 RB751V_SOD323
3
LINK_LED100#
EPHY_AGND EPHY_AVDD
BCM 4401L
2
2
65 68 XTAL_AVDD XTAL_AVSS
114 25 56 VESD1 VESD2 VESD3
91 92 REG_VOUT1 REG_VOUT2
96 97 REG_AVDD1 REG_AVDD2
106 79 94 NC10 VDDIO1 VDDIO2
115 125 19 30 40 52 7 VDDBUS1 VDDBUS2 VDDBUS3 VDDBUS4 VDDBUS5 VDDBUS6 VDDBUS7
1
LINK_LED10# LINK_LED100# ACTLED#
1
67 66
75 76 77 78
47K
B
Q16 2N7002_SOT23
D9
2
22
<19,25,26,30> CLKRUN#
LED0_L LED1_L LED2_L LED3_L
D
2 G
<26> WLAN_LINK_10_LED
R32 10K_0402_5%
1
LAN_AD17
117 118 119 121 113 5
Broadcom
R31 10K_0402_5%
2
PCIRST#
0,16,18,23,25,26,30,33> PCIRST# <15> CLK_PCI_LAN <18> GNT#0 <18> REQ#0 <31> LAN_PME#
R33 10K_0402_5%
(LAN_10LINK)
1 2 D8 RB751V_SOD323
2
4 18 32 43 20 21 23 26 27 28 29 31 116
<18,23,25,26,33> C/BE#3 <18,23,25,26,33> C/BE#2 <18,23,25,26,33> C/BE#1 <18,23,25,26,33> C/BE#0 <18,23,25,26,33> PCI_FRAME# <18,23,25,26> PCI_IRDY# <18,23,25,26,33> PCI_TRDY# <18,23,25,26> PCI_DEVSEL# <18,23,25,26> PCI_STOP# <18,23,25,26> PCI_PERR# <18,23,25,26> PCI_SERR# <18,23,25,26> PCI_PAR <18> PIRQB#
PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0
LINK_LED10#
2
C
122 123 124 126 127 128 1 3 6 8 9 10 11 14 15 16 33 34 36 37 38 39 41 42 45 48 49 50 51 53 54 55
VDDCORE1 VDDCORE2 VDDCORE3
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
112 17 44
1
+3VAUXLAN
U11
B
WLAN_LINK_10_LDE LINK_LED10# WLAN_ACT_LED
+3VAUXLAN
Place close to pin 69
1
AD [0..31]
<18,23,24,25,26,33> AD[0..31]
+3VAUXLAN
2 1 L39 BLM11A121SPT_0603
+3V +3VAUXLAN
15 mil
LED (JP28) ORANGE (100M)
+3VAUXLAN
+3VWOL
2
R462 @0_0603_5%
Place close to pin 57
2
+3VS
2
2
LOM
WLAN_LINK_80211A LINK_LED100#
WLAN_LINK_80211A
L7 @BLM11A121SPT_0603 2 1
+3VALW +3VWOL
C70 0.1U_0402_16V4Z
C82
2 0.1U_0402_16V4Z
1
+3VAUXLAN
C95
1
0.1U_0402_16V4Z
D
R461 0_0603_5% 1 2
C72 2
WLAN
0.1U_0402_16V4Z 1
1
2
2
0.1U_0402_16V4Z 1
1
1
0.1U_0402_16V4Z 1
C211 1000P_1808_2KV7K
1
C212 1000P_1808_2KV7K
1
CLK_PCI_LAN A
2 AD17
1 R64
1
LAN_AD17 2 100_0402_5%
2
A
+3VAUXLAN R52 33_0402_5%
C79 22P_0402_50V8J
LAN_RX+ LAN_RXLAN_TX+ LAN_TX-
R53 R51 R42 R46
2 2 2 2
1 1 1 1
49.9_0805_1% 49.9_0805_1% 49.9_0805_1% 49.9_0805_1%
Chassis GND & Digital GND Short Together 1
2
1 C56 0.1U_0402_16V4Z
2
Dell-Compal Confidential
C84 0.1U_0402_16V4Z
Compal Electronics, Inc.
Place close to U11
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5
4
3
2
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet 1
22
of
47
A
B
C
D
E
This page POP with 845PE for EXT. AD [0..31]
<18,22,24,25,26,33> AD[0..31] 2 1 R73 @402K_0603_1%
R59 @0_0402_5% 1
P10
2
PHY_CNA
P17
V10 W10 P9
PCI4510_R0
W13
PCI4510_R1
V13
1
R63 R58 1 2@0_0402_5%
R71
P HY_CPS
2
CNA
PC0 PC1 PC2
PCI4510
R0
VCCCB_G14 VCCCB_A11 VCCP_L01 VCCP_W05
C115 2@10U_1206_10V4Z
VDPLL 1
1
2
2
C103
[email protected]_0402_25V4Z
G14 A11 +3V_CBSD L1 W5
V12
IEEE1394_TPA0-
W12 V15
1
IEEE1394_TPB0+
V11
IEEE1394_TPB0-
W11
IEEE1394_TPB1+
[email protected]_0402_16V4Z IEEE1394_TPB1-
V14 W14
IEEE1394_TPBIAS0 2 C98
1
TPA0VCCD0# VCCD1#
U12
IEEE1394_TPBIAS1 2@1U_0603_10V4Z
U15
VDPLL
P15
N14
C78
FILTER0 FILTER1
[email protected]_0402_10V6K
T19 R17 N15 M14 N17 N18 N19 M15 M17 M18 M19
3
+3V_CBSD
CBS_MFUNC1
1 R23
CBS_MFUNC2
1 R38
CBS_MFUNC4
1 R36
CBS_MFUNC5
1 R39
CBS_MFUNC6
1 R26
VCCD0# VCCD1#
<24,25> <24,25>
A4 C5
VPPD0 VPPD1
<24,25> <24,25>
CLK_PCI_PCM
TPA1-
VPPD0# VPPD1#
R47 @33_0402_5%
B7 C7 F7 A6 B6 E7 C6
2 2@10K_0402_5% 2 2@10K_0402_5% 2 2@10K_0402_5% 2 2@10K_0402_5% 2 2@10K_0402_5%
TPB0-
GND_E01 GND_K01 GND_N01 GND_W06 GND_P19 GND_K19 GND_G19 GND_A15 GND_A10 GND_A7
TPB1+ TPB1TPBIAS0 TPBIAS1
AVD2 AVD3 AVD4
SUSPEND#
AGND2 AGND3 AGND4
RI_OUT#/PME# SPKROUT
VDPLL
VSPLL FILTER0 FILTER1
INTA#/MFUNC0 INTB#/MFUNC1 MFUNC2 MFUNC3 MFUNC4 LEDSKT/MFUNC5 MFUNC6
H5
2
C75 @22P_0402_50V8J
G3
PCM_SUSP# <24,25,30> R57 2 1 2@0_0402_5% PCM_SPK#
J3 E2
PCM_PME# <25,31> PCM_SPK# <25,28>
PIRQA# CBS_MFUNC1 CBS_MFUNC2
F5 G6 F3 F2 G5 F1 H6
SCL SDA
PIRQA# SIRQ
CBS_MFUNC4 CBS_MFUNC5 CBS_MFUNC6
<18,25> <18,25,30>
PHY_TEST_MA TEST0 TEST1 CLK48_RSVD
SC_CD# SC_RST SC_CLK SC_DATA SC_PWR SC_MODE SC_FCB
P18
PHY_TEST_MA
U10
CBS_TEST0
R10
CBS_TEST1
L6 P2 U5 V7
C/BE#3 C/BE#2 C/BE#1 C/BE#0
<18,22,25,26> PCI_PAR
W4
<18,22,25,26> PCI_DEVSEL# <18,22,25,26,33> PCI_FRAME# <18,25> GNT#2
R2 N5 J1
<18,22,25,26> PCI_IRDY# <18,22,25,26> PCI_PERR# <18,25> REQ#2 <18,22,25,26> PCI_SERR# <18,22,25,26> PCI_STOP# <18,22,25,26,33> PCI_TRDY# <6,10,16,18,22,25,26,30,33> PCIRST#
P3 R3 J2 T1 P5 P6 H3
<16,24,25> V_PRST#
H2
<24,25> PCM_ID
CBS_SCL CBS_SDA
E3 D1
<18,22,25,26,33> <18,22,25,26,33> <18,22,25,26,33> <18,22,25,26,33>
CC/BE3#/REG# CC/BE2#/A12 CC/BE1#/A8 CC/BE0#/CE1#
C/BE3# C/BE2# C/BE1# C/BE0#
CRESET CFRAME#/A23 CIRDY#/A15 CTRDY#/A22 CDEVSEL#/A21 CSTOP#/A20 CPERR#/A14 CSERR#/WAIT# CPAR/A13 CREQ#/INPACK# CGNT#/WE# CCLK/A16
PCI_PAR
R22 2 1 2@0_0402_5%
1V8_VR_EN#
+3V_CBSD
MC_RSVD1 MC_RSVD3 MC_RSVD4 MC_RSVD5 MC_RSVD6 MC_RSVD7 MC_RSVD8 MC_RSVD9 MC_RSVD10
E1 K1 N1 W6 P19 K19 G19 A15 A10 A7
2 R44 2 R61 2 R60
PCM_ID L5
H1
<15,25> CLK_PCI_PCM
XI
XO
R18
1 C223 2@ 1U_0603_10V4Z
DEVSEL# FRAME# GNT# IRDY# PERR# REQ# SERR# STOP# TRDY# PCI_RESET#
CSTSCHG/BVD1 CCLKRUN#/WP
CBS_CSTSCHNG CBS_CCLKRUN#
CBLOCK#/A19 CINT#/READY
CVS2/VS2# CVS1/VS1#
IDSEL
CRSVD/D2 CRSVD/A18 CRSVD/D14
PCICLK
F10 C9 L17
CBS_CAUDIO CBS_CCD2# CBS_CCD1#
F12 B10
CBS_CVS2 CBS_CVS1
F8 F17 J18
CBS_RSVD/D2 CBS_RSVD/A18 CBS_RSVD/D14
2
CBS_CRST# <24,25> CBS_CFRAME# <24,25> CBS_CIRDY# <24,25> CBS_CTRDY# <24,25> CBS_CDEVSEL# <24,25> CBS_CSTOP# <24,25> CBS_CPERR# <24,25> CBS_CSERR# <24,25> CBS_CPAR <24,25> CBS_CREQ# <24,25> CBS_CGNT# <24,25> CBS_CCLK_INTERNAL <24,25> CBS_CSTSCHNG <24,25> CBS_CCLKRUN# <24,25> CBS_CBLOCK# <24,25> CBS_CINT# <24,25> CBS_CAUDIO <24,25> CBS_CCD2# <24,25> CBS_CCD1# <24,25> CBS_CVS2 <24,25> CBS_CVS1 <24,25> CBS_RSVD/D2 <24,25> CBS_RSVD/A18 <24,25> CBS_RSVD/D14 <24,25> 3
R19
PCI4510XO
U3 8 7 6 5
R199 2@ 56.2_0603_1%
[email protected]_16P X1 1 2 C83
R198 2@ 56.2_0603_1%
1
2
JP2 1 2 3 4
TPB0+ TPA0-
@BTS0402-01_8P TPA0+
C106 2@22P_0402_50V8J R197 2@ 56.2_0603_1%
2@ 56.2_0603_1%
GND1 GND2 GND3 GND4
RP1 1 2 3 4
2
1 2 3 4
5 6 7 8
R196
2
2
1
IEEE1394_TPB0IEEE1394_TPB0+ IEEE1394_TPA0IEEE1394_TPA0+
TPB0-
1 2 3 4
2@AMP_440168-2_4P
8 7 6 5
[email protected]_0402_16V4Z 1
C108 2
A9 B9
<24,25> <24,25> <24,25> <24,25>
1 C101
2
1 C102
2
2
C109
[email protected]_0402_16V4Z
1 2@ 220_0402_5% 1 2@ 220_0402_5%
CBS_SCL
2@0_8P4R_1206_5%
1
2 R21 2 R37
1
CBS_SDA C216 2@ 270P_0603_50V8J
4
R194
[email protected]_0603_1%
2
2
2
C114 2@10U_1206_10V4Z
CBS_CRST# CBS_CFRAME# CBS_CIRDY# CBS_CTRDY# CBS_CDEVSEL# CBS_CSTOP# CBS_CPERR# CBS_CSERR# CBS_CPAR CBS_CREQ# CBS_CGNT# CBS_CCLK_INTERNAL
E18 CBS_CBLOCK# C10 CBS_CINT#
CAUDIO/BVD2 CCD2/CD2# CCD1/CD1#
G_RST#
2
+3V_CBSA
1
B13 B15 F13 E14 A16 E17 F15 E10 F14 B12 D19 C15
CBS_CC/BE3# CBS_CC/BE2# CBS_CC/BE1# CBS_CC/BE0#
IEEE1394_TPBIAS0 PCI4510XI
2@PCI4510GHK_PBGA209
+3V
1
CBS_CC/BE3# CBS_CC/BE2# CBS_CC/BE1# CBS_CC/BE0#
2@PCI4510GHK_PBGA209
1
[email protected]_0402_5% 1 2@200_0402_5% 1 2@200_0402_5%
F6
2@22P_0402_50V8J
4
B11 C14 G15 J15
1
1
TPB0+
POP for 845PE
2@BLM21A601SPT_0805 L10 1 2
CBS_CAD31 CBS_CAD30 CBS_CAD29 CBS_CAD28 CBS_CAD27 CBS_CAD26 CBS_CAD25 CBS_CAD24 CBS_CAD23 CBS_CAD22 CBS_CAD21 CBS_CAD20 CBS_CAD19 CBS_CAD18 CBS_CAD17 CBS_CAD16 CBS_CAD15 CBS_CAD14 CBS_CAD13 CBS_CAD12 CBS_CAD11 CBS_CAD10 CBS_CAD9 CBS_CAD8 CBS_CAD7 CBS_CAD6 CBS_CAD5 CBS_CAD4 CBS_CAD3 CBS_CAD2 CBS_CAD1 CBS_CAD0
1
U11 R12 R13
2
E6 B5
TPA1+
VR_EN# R11 U13 U14
+3V_CBSA
1
Place close to pin H1
2
[email protected]_0402_16V4Z
2
2 C89
2
[email protected]_0402_16V4Z
1 C73
E8 C8 B8 E9 F9 F11 E11 C11 A12 C12 E12 C13 A14 E13 B14 F18 G17 F19 G18 H15 H14 H17 H18 J14 J17 K14 J19 K17 K15 L14 K18 L15
1
1 2@1K_0402_5% 1 2@1K_0402_5%
C53 1
G2 L18
PCI4510
CAD31/D10 CAD30/D9 CAD29/D1 CAD28/D8 CAD27/D0 CAD26/A0 CAD25/A1 CAD24/A2 CAD23/A3 CAD22/A4 CAD21/A5 CAD20/A6 CAD19/A25 CAD18/A7 CAD17/A24 CAD16/A17 CAD15/IOWR# CAD14/A9 CAD13/IORD# CAD12/A11 CAD11/OE# CAD10/CE2# CAD9/A10 CAD8/D15 CAD7/D7 CAD6/D13 CAD5/D6 CAD4/D12 CAD3/D5 CAD2/D11 CAD1/D4 CAD0/D3
2
W15
1.8V_G02 1.8V_L18
TPA0+
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
1
1
1
L11 1 2 2@BLM21A05 _0805
1
IEEE1394_TPA0+ 2@0_0402_5%
2
+3V_CBSA
G1 M1 R1 W8 L19 H19 E19 A13 A8 A5 CBS_VCC
R1
[email protected]_0603_1%
2 R65 2 R56
VCC_G01 VCC_M01 VCC_R01 VCC_W08 VCC_L19 VCC_H19 VCC_E19 VCC_A13 VCC_A08 VCC_A05
CPS
1
R72 2@0_0402_5%
U35B
1
R50 2@43K_0402_5% CBS_PC0 CBS_PC1 CBS_PC2
2
1
R68 @0_0402_5%
2
2
2
J5 J6 K2 K3 K5 K6 L2 L3 M2 M3 M6 M5 N2 N3 N6 P1 R6 P7 V5 U6 V6 R7 P8 U7 W7 R8 U8 V8 W9 V9 U9 R9
2
2
R69 @0_0402_5%
1
1
2
2
R70 2@1K_0402_5%
CBS_CAD[0..31] <24,25>
U35A AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
+3V_CBSD
1
+3V_CBSD
<18,22,24,25,26,33> AD[0..31]
+3V_CBSA
Dell-Compal Confidential
[email protected]_0402_16V4Z
[email protected]_0402_16V4Z
Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
23
of
47
A
B
C
D
E
PCMCIA Power Controller
+12VALW
1
CBS_VCC
1
C31 U7 0.1U_0603_50V4Z
2
9
VCC VCC VCC
12V
13 12 11
C18 4.7U_0805_10V4Z
2
CBS_VPP
1
L9 BLM21A601SPT_0805 1 2
+5VALW 1 VPP 5 6
1
2
C25 0.1U_0402_16V4Z
2 VCCD0 VCCD1 VPPD0 VPPD1
GND
3.3V 3.3V
7
C21 2 0.1U_0402_16V4Z
16
3 4
1
OC
SHDN
+3VALW
+3V
10
5V 5V 1 2 15 14
C23 0.1U_0402_16V4Z
1
2
VCCD0# VCCD1# VPPD0 VPPD1
VCCD0# VCCD1# VPPD0 VPPD1
<23,25> <23,25> <23,25> <23,25>
C71 0.1U_0402_16V4Z
C85 10U_1206_10V4Z
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
C36 0.1U_0402_16V4Z
2
C17 1U_0603_10V4Z
1 C60 0.01U_0402_25V4Z C30 1U_0603_10V4Z
2
C92 0.1U_0402_16V4Z
V_PRST# <16,23,25>
CBS_VCCL +5VALW 1
C34 0.1U_0402_16V4Z
C49 0.1U_0402_16V4Z
TPS2211AIDBR_SSOP16
2
1
C51 10U_1206_10V4Z
1
+3V_CBSD C90 0.1U_0402_16V4Z
C81 0.1U_0402_16V4Z
8
V_PRST#
+3VALW
C57 0.1U_0402_16V4Z
CBS_VCC
1
2
2
1
C50 4.7U_0805_10V4Z
2
2
1 C37 0.1U_0402_16V4Z
Near U35 Pin G14
2
C35 0.1U_0402_16V4Z
Near U35 Pin A11
CBS_VPP C24 0.01U_0402_25V4Z
1
1
2
2
C26 1U_0603_10V4Z CBS_VCC
1 2 L6 KC FBM-L11-201209-221LMAT_0805
CBS_VCCL
+3V_CBSD
1 2 L5 @KC FBM-L11-201209-221LMAT_0805
CardBus Socket
2 C19 1000P_0402_50V7K 2 1
1
1 C76 0.1U_0402_16V4Z
2
C93 0.1U_0402_16V4Z
Near U35 Pin W5
JP18
Near U35 Pin L1
3
<23,25> CBS_CAD0 <23,25> CBS_CAD1 <23,25> CBS_CAD3 <23,25> CBS_CAD5 <23,25> CBS_CAD7 <23,25> CBS_CC/BE0# <23,25> CBS_CAD9 <23,25> CBS_CAD11 <23,25> CBS_CAD12 <23,25> CBS_CAD14 <23,25> CBS_CC/BE1# <23,25> CBS_CPAR <23,25> CBS_CPERR# <23,25> CBS_CGNT# <23,25> CBS_CINT# CBS_VCCL CBS_VPP <23,25> <23,25> <23,25> <23,25> <23,25> <23,25> <23,25> <23,25> <23,25> <23,25> <23,25> <23,25> <23,25> <23,25>
CBS_CIRDY# CBS_CC/BE2# CBS_CAD18 CBS_CAD20 CBS_CAD21 CBS_CAD22 CBS_CAD23 CBS_CAD24 CBS_CAD25 CBS_CAD26 CBS_CAD27 CBS_CAD29 CBS_RSVD/D2 CBS_CCLKRUN#
4
CBS_CAD0 CBS_CAD1 CBS_CAD3 CBS_CAD5 CBS_CAD7 CBS_CC/BE0# CBS_CAD9 CBS_CAD11 CBS_CAD12 CBS_CAD14 CBS_CC/BE1# CBS_CPAR CBS_CPERR# CBS_CGNT# CBS_CINT# CBS_CCLK CBS_CIRDY# CBS_CC/BE2# CBS_CAD18 CBS_CAD20 CBS_CAD21 CBS_CAD22 CBS_CAD23 CBS_CAD24 CBS_CAD25 CBS_CAD26 CBS_CAD27 CBS_CAD29 CBS_RSVD/D2 CBS_CCLKRUN#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 69 71 73 75 77 79 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 GND GND GND GND GND GND GND
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 GND GND GND GND GND GND GND
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 70 72 74 76 78 80 82
CBS_CCD1# CBS_CAD2 CBS_CAD4 CBS_CAD6 CBS_RSVD/D14 CBS_CAD8 CBS_CAD10 CBS_CVS1 CBS_CAD13 CBS_CAD15 CBS_CAD16 CBS_RSVD/A18 CBS_CBLOCK# CBS_CSTOP# CBS_CDEVSEL# CBS_CTRDY# CBS_CFRAME# CBS_CAD17 CBS_CAD19 CBS_CVS2 CBS_CRST# CBS_CSERR# CBS_CREQ# CBS_CC/BE3# CBS_CAUDIO CBS_CSTSCHNG CBS_CAD28 CBS_CAD30 CBS_CAD31 CBS_CCD2#
CBS_CCD1# <23,25> CBS_CAD2 <23,25> CBS_CAD4 <23,25> CBS_CAD6 <23,25> CBS_RSVD/D14 <23,25> CBS_CAD8 <23,25> CBS_CAD10 <23,25> CBS_CVS1 <23,25> CBS_CAD13 <23,25> CBS_CAD15 <23,25> CBS_CAD16 <23,25> CBS_RSVD/A18 <23,25> CBS_CBLOCK# <23,25> CBS_CSTOP# <23,25> CBS_CDEVSEL# <23,25> CBS_VCCL CBS_VPP CBS_CTRDY# <23,25> CBS_CFRAME# <23,25> CBS_CAD17 <23,25> CBS_CAD19 <23,25> CBS_CVS2 <23,25> CBS_CRST# <23,25> CBS_CSERR# <23,25> CBS_CREQ# <23,25> CBS_CC/BE3# <23,25> CBS_CAUDIO <23,25> CBS_CSTSCHNG <23,25> CBS_CAD28 <23,25> CBS_CAD30 <23,25> CBS_CAD31 <23,25> CBS_CCD2# <23,25>
3
CBS_CCLK
<18,22,23,25,26> AD20
AD20
1 R27
2 47_0402_5%
1 R41
PCM_ID 2 100_0402_5%
2 R40
<23,25,30> PCM_SUSP#
CBS_CCLK_INTERNAL <23,25>
PCM_ID
<23,25>
1 +3V_CBSD 10K_0402_5%
1
2
C107 1000P_0402_50V7K
4
Dell-Compal Confidential
JAE JC21-BRB-E500
Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
24
of
47
A
B
C
D
E
This page POP with 845GL for INT. CBS_CAD[0..31]
CBS_CAD[0..31] <23,24>
U34B
PCI1510
1
U34A
<18,22,23,26,33> <18,22,23,26,33> <18,22,23,26,33> <18,22,23,26,33>
47 37 26 13
C/BE#0 C/BE#1 C/BE#2 C/BE#3
<23,24> PCM_ID
PCM_ID
14
<15,23> CLK_PCI_PCM
20
<18,22,23,26> PCI_PAR <18,22,23,26> PCI_SERR# <18,22,23,26> PCI_PERR# <18,22,23,26> PCI_STOP# <18,22,23,26> PCI_IRDY# <18,22,23,26,33> PCI_TRDY# <6,10,16,18,22,23,26,30,33> PCIRST# <18,22,23,26> PCI_DEVSEL# <18,22,23,26,33> PCI_FRAME# <18,23> GNT#2 <18,23> REQ#2
35 34 33 31 28 29 19 30 27 2 1
Multifunction& Miscellaneous MF0/INTA# MF1 MF2/DMAREQ# MF3/IRQSER MF4/RI_OUT# MF5/DMAGNT# MF6/CLKRUN#
RI_OUT#/PME# SPKROUT SUSPEND# CLK_48M_RSVD VR_EN# VR_PORT
58 59 63 64 67 68 69
CBS_1510MF1 CBS_1510MF2 CBS_1510MF4 CBS_1510MF5
C/BE0# C/BE1# C/BE2# C/BE3#
VCCP VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 GND GND GND GND GND GND GND GND
GND
IDSEL
PIRQA#
<18,23>
SIRQ
<18,23,30>
CLKRUN# <19,22,26,30>
57 61 65 85
PCM_PME# <23,31> PCM_SPK# <23,28> PCM_SUSP# <23,24,30>
125 62 1
2
PCI PWR
PCI BUS
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
CORE LOGIC PWR
56 55 53 52 51 50 49 48 46 45 44 43 42 41 39 38 25 24 23 22 18 17 16 15 11 10 9 7 6 5 4 3
C91
[email protected]_0402_16V4Z +3V_CBSD
36 54 70 104 126 137 12 32
CBS_1510MF1
+3V_CBSD
1 R75 1 R76 1 R66 1 R62
CBS_1510MF2 CBS_1510MF4 CBS_1510MF5
8 21 40 60 80 93 112 132
PCLK PAR SERR# PERR# STOP# IRDY# TRDY# PRST# DEVSEL# FRAME# GNT# REQ#
VCCD0# VCCD1# VPPD0 VPPD1
Card PWR S/W
2
3
PCI1510
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
GRST#
73 74 71 72
66
VCCD0# VCCD1# VPPD0 VPPD1
2 1@10K_0402_5% 2 1@10K_0402_5% 2 1@10K_0402_5% 2 1@10K_0402_5%
PC CARD / CARD BUS INTERFACE
<18,22,23,24,26,33> AD[0..31]
A_D3/CAD0 A_D4/CAD1 A_D11/CAD2 A_D5/CAD3 A_D12/CAD4 A_D6/CAD5 A_D13/CAD6 A_D7/CAD7 A_D15/CAD8 A_A10/CAD9 A_CE2#/CAD10 A_OE#/CAD11 A_A11/CAD12 A_IORD#/CAD13 A_A9/CAD14 A_IOWR#/CAD15 A_A17/CAD16 A_A24/CAD17 A_A7/CAD18 A_A25/CAD19 A_A6/CAD20 A_A5/CAD21 A_A4/CAD22 A_A3/CAD23 A_A2/CAD24 A_A1/CAD25 A_A0/CAD26 A_D0/CAD27 A_D8/CAD28 A_D1/CAD29 A_D9/CAD30 A_D10/CAD31 A_A18/RSVD A_D14/RSVD A_D2/RSVD A_CE1#/CC/BE0# A_A8/CC/BE1# A_A12/CC/BE2# A_REG#/CC/BE3# A_A13/CPAR A_A14/CPERR# A_A15/CIRDY# A_A16/CCLK
A_A19/CBLOCK# A_A20/CSTOP# A_A21/CDEVSEL# A_A22/CTRDY# A_A23/CFRAME# A_BVD1/CSTSCHG A_BVD2/CAUDIO A_READY/CINT# A_WAIT#/CSERR# A_WP/CCLKRUN#
<23,24> <23,24> <23,24> <23,24>
A_CD1#/CCD1# A_CD2#/CCD2# A_INPACK/CREQ# A_WE#/CGNT# A_VS1#/CVS1 A_VS2#/CVS2
V_PRST# <16,23,24> A_RESET/CRST# VCC_CARD
76 78 77 81 79 83 82 86 87 89 90 91 92 94 96 95 97 114 115 116 118 120 121 123 127 128 129 139 140 141 142 144
CBS_CAD0 CBS_CAD1 CBS_CAD2 CBS_CAD3 CBS_CAD4 CBS_CAD5 CBS_CAD6 CBS_CAD7 CBS_CAD8 CBS_CAD9 CBS_CAD10 CBS_CAD11 CBS_CAD12 CBS_CAD13 CBS_CAD14 CBS_CAD15 CBS_CAD16 CBS_CAD17 CBS_CAD18 CBS_CAD19 CBS_CAD20 CBS_CAD21 CBS_CAD22 CBS_CAD23 CBS_CAD24 CBS_CAD25 CBS_CAD26 CBS_CAD27 CBS_CAD28 CBS_CAD29 CBS_CAD30 CBS_CAD31
99 84 143
CBS_RSVD/A18 CBS_RSVD/D14 CBS_RSVD/D2
88 98 113 124 100 102 110 107
CBS_CC/BE0# CBS_CC/BE1# CBS_CC/BE2# CBS_CC/BE3# CBS_CPAR CBS_CPERR# CBS_CIRDY# CBS_CCLK_INTERNAL
101 103 106 108 111 135 134 131 133 136
CBS_CBLOCK# CBS_CSTOP# CBS_CDEVSEL# CBS_CTRDY# CBS_CFRAME# CBS_CSTSCHNG CBS_CAUDIO CBS_CINT# CBS_CSERR# CBS_CCLKRUN#
75 138
CBS_CCD1# CBS_CCD2#
122 105
CBS_CREQ# CBS_CGNT#
130 117
CBS_CVS1 CBS_CVS2
119 109
CBS_CRST#
1
CBS_RSVD/A18 <23,24> CBS_RSVD/D14 <23,24> CBS_RSVD/D2 <23,24>
2
CBS_CC/BE0# <23,24> CBS_CC/BE1# <23,24> CBS_CC/BE2# <23,24> CBS_CC/BE3# <23,24> CBS_CPAR <23,24> CBS_CPERR# <23,24> CBS_CIRDY# <23,24> CBS_CCLK_INTERNAL <23,24> CBS_CBLOCK# <23,24> CBS_CSTOP# <23,24> CBS_CDEVSEL# <23,24> CBS_CTRDY# <23,24> CBS_CFRAME# <23,24> CBS_CSTSCHNG <23,24> CBS_CAUDIO <23,24> CBS_CINT# <23,24> CBS_CSERR# <23,24> CBS_CCLKRUN# <23,24> CBS_CCD1# <23,24> CBS_CCD2# <23,24> CBS_CREQ# <23,24> CBS_CGNT# <23,24> CBS_CVS1 <23,24> CBS_CVS2 <23,24> CBS_CRST# <23,24>
3
CBS_VCC
1@ PCI1510PGE_PQFP144 1@ PCI1510PGE_PQFP144
4
4
Dell-Compal Confidential Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
25
of
47
5
4
3
2
1
Place close to pin 25
MINI PCI TYPE III
2 R428 33_0402_5%
+3VMINI
JP24
+3VMINI
+3VAUXMINI
1
<22> W LAN_ACT_LED <30> RADIO_DISABLE# <18>
PIRQD#
<15> CLK_PCI_MINI <18>
REQ#1 AD31 AD29 AD27 AD25 C/BE#3 AD23
C
AD21 AD19 AD17 C/BE#2 <18,22,23,25> P C I_ IRDY# <19,22,25,30> CLKRUN# <18,22,23,25> PCI_SERR# <18,22,23,25> PCI_PERR#
C/BE#1 AD14 AD12 AD10 A D8 A D7 A D5 A D3 +5VMINI
B
+5VMINI
A D1
TIP
RING
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123
8PMJ-3 8PMJ-6 8PMJ-7 8PMJ-8 LED1_GRNP LED1_GRNN CHSGND INTB# 3.3V RESERVED GROUND CLK GROUND REQ# 3.3V AD31 AD29 GROUND AD27 AD25 RESERVED C/BE#3 AD23 GROUND AD21 AD19 GROUND AD17 C/BE#2 IRDY# 3.3V CLKRUN# SERR# GROUND PERR# C/BE#1 AD14 GROUND AD12 AD10 GROUND AD8 AD7 3.3V AD5 RESERVED AD3 5V AD1 GROUND AC_SYNC AC_SDATA_IN AC_BIT_CLK AC_CODEC_ID1# MOD_AUDIO_MON AUDIO_GND SYS_AUDIO_OUT AUDIO_OUTGND AUDIO_GND RESEVED VCC5VA
127
127
D
2
2
8PMJ-1 8PMJ-2 8PMJ-4 8PMJ-5 LED2_YELP LED2_YELN REVERVED 5V INTA# RESERVED 3.3VAUX RST# 3.3V GNT# GROUND PME# RESERVED AD30 3.3V AD28 AD26 AD24 IDSEL GROUND AD22 AD20 PAR AD18 AD16 GROUND FRAME# TRDY# STOP# 3.3V DEVSEL# GROUND AD15 AD13 AD11 GROUND AD09 C/BE#0 3.3V AD6 AD4 AD2 AD0 RESERVED_WIP RESERVED_WIP GROUND M66EN AC_SDATA_OUT AC_CODEC_ID0# AC_RESET# RESERVED GROUND SYS_AUDIO_IN AUDIO_INGND AUDIO_GND MPCIACT# 3.3VAUX
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124
128
128
C/BE#[0..3]
<18,22,23,25,33> C/BE#[0..3]
1
D
AD[0..31]
<18,22,23,24,25,33> AD[0..31]
CLK_PC I_MINI
1
+3VAUXMINI
C614 22P_0402_50V8J
W LAN_LINK_10_LED <22> W LAN_LINK_80211A <22> +5VMINI PIRQC#
1 R400
2 +3VALW @0_0603_5%
1 R399
2 +3V 2@ 0_0603_5%
<18>
PCIRST#
<6,10,16,18,22,23,25,30,33>
GNT#1
<18>
MINI_PME# <31> AD30
W LAN_LINK_80211A
2 R398
1 100K_0402_5%
AD28 AD26 AD24
W LAN_LINK_10_LED
2 R397
1 100K_0402_5%
W LAN_ACT_LED
2 R429
1 100K_0402_5%
M66EN
2 R401
1 2@ 1K_0402_5%
MPCIACT#
2 R405
1 +3VAUXMINI 2@ 100K_0402_5%
AD18 2 2@ 100_0402_5%
1 R403 AD22 AD20
IDSEL
AD18
PCI_PAR <18,22,23,25>
AD18 AD16
C
PCI_FRAME# <18,22,23,25,33> PCI_TRDY# <18,22,23,25,33> PCI_STOP# <18,22,23,25> PCI_DEVSEL# <18,22,23,25> AD15 AD13 AD11 A D9 C/BE#0 A D6 A D4 A D2 A D0 DIMM_SMCLK <12,13,15,18> DIMM_SMDATA <12,13,15,18> +3VAUXMINI
M66EN
+5VMINI
+5VS L36 1 2 2@ BLM21A05 _0805
30mil
1
1
2@ 0.1U_0402_16V4Z 2
2
C600
1 C596 2@ 0.1U_0402_16V4Z
B
1 C616
2
2
C610 2@ 1000P_0402_50V7K
MPCIACT# 2@ 0.1U_0402_16V4Z
2@AMP 1318914
+3VMINI
+3VS
[email protected]_0402_16V4Z
1 C613 2@ 10U_1206_10V4Z 2
WIRELESS SUPPORT ONLY
1
2@ 0.1U_0402_16V4Z 30mil 1
1 C612
2
A
1 C599
2
1 C598
2
2
2
L35 2@ BLM21A05 _0805 C609 2@ 1000P_0402_50V7K
A
2@ 0.1U_0402_16V4Z
Dell-Compal Confidential Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: 5
4
3
2
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 ¬P 期五, 四月 25, 2003
Sheet 1
26
of
47
A
B
C
D
E
+5VALW
F
G
+5VDDA
H
+5VDDA
U26 1
W=40Mil 1
1
2
2
1 3
C564 @4.7U_0805_10V4Z
C562 0.1U_0402_16V4Z
VOUT
5
VIN
1 BYPASS
2
C558
2
HP_OUT_R C556
1
C555
1
EN GND
1
4 2
0.1U_0402_16V4Z
C481 2
2
HP_OUT_L
C554 4.7U_0805_10V4Z
1
1
2
C165 1000P_0402_50V7K
2
TPS793475DBV_SOT23-5
C134 1000P_0402_50V7K 1 2
1
4.7U_0805_10V4Z 0.1U_0402_16V4Z
0.1U_0603_50V4Z
<16,30,33,38> SUSP#
1 2 L30 BLM21A05 _0805
+5VDDA
+3VCC
1
1
1
1
1
1
R345 2 0_0805_5%
2
2
C551 4.7U_0805_10V4Z
2
C484
MAX 80mA
C491
2
CLK_CODEC_14M
1 1
C541 0.1U_0402_16V4Z
Place close to pin 2
C486 1000P_0402_50V7K 2 1
+3VS
1
0.1U_0402_16V4Z
2
2
C478 4.7U_0805_10V4Z
R341 @10_0402_5%
2
C487 1000P_0402_50V7K
2
AVDD_AC97
16 1
0.1U_0402_16V4Z
17 23 24
<28>
MONO_IN
MONO_IN 1 R364 47K_0402_5%
1 C549 C D_R_R 1 C547 CD_GNA 1 C546 <28>
2
18 1U_0603_10V4Z 20 1U_0603_10V4Z 2 19 1U_0603_10V4Z 21 MICIN 2
1
2
MDSPK
C552 2700P_0603_50V7K
1 C557 0.033U_0402_16V4Z
2
9
1
VIDEO_L
MONO_OUT
VIDEO_R
HP_OUT_L
LIN_IN_L
HP_OUT_R
1 C545 1 C550 1 C553
2 2 2
12 1U_0603_10V4Z 11
<19,29> IAC_SYNC
10
<19,29> IAC_SDATAO
5
2 R344 2 R343 <28>
EAPD
1 1@1K_0402_5% @1K_0402_5% EAPD
45 46
1 10K_0402_5%
48
2 R339
47
4 7
CD_L
8
SDATA_IN CD_R
2
@1000P_0402_50V7K
R350 1 2 @100K_0402_5% MD_MIC <29>
1U_0603_10V4Z
HP_OUT_R <28> 1 R359 1 R357
2 22_0402_5% 2 47_0402_5%
IAC_BITCLK <19,29>
2 C500 @27P_0402_50V8J
IAC_SDATA_IN0 <19>
2
XTL_IN
2
HP_OUT_L <28>
CD_GNA
1 R342
1 C485
2 @0_0402_5%
CLK_CODEC_14M <15>
2 22P_0402_50V8J
X4 24.576MHz_16P
MIC1
29
AFLT1
PC_BEEP
1
3
XTL_OUT
30
AFLT2
1 C499 1 C493
RESET#
3
27
REFFLT SYNC
1
32
FLT3D SDATA_OUT ID0# ID1# EAPD
2
C542 22P_0402_50V8J
2 820P_0603_50V7K 2 820P_0603_50V7K
28
VREFOUT
31 33 34 43 44
BPCFG_00/NC_50 FLTI_00/NC_50 FLTO_00/NC_50 NC_00/GPIO0_50 NC_00/GPIO1_50
S/PDIF_OUT NC_00/HP_COMM_50 GND AGND GND AGND
2 C490 @1U_0603_10V4Z 0.1U_0402_16V4Z C523
SPK_SHUTDOWN#
SPK_SHUTDOWN# <28> C489 @4.7U_0805_10V4Z
40 26 42
1
1
2
2
C498 1U_0603_10V4Z
1
1
2
2
short the digital ground and analong ground
R354 @100K_0402_5%
C492 @1U_0603_10V4Z
1
2
ID0#
2
R366 @6.8K_0603_1% 4
1 C483
1 6
CD_GNA
1
R367 0_0402_5%
37
MDMIC
1 C476
C479 @10P_0402_50V8K
C471 1U_0603_10V4Z
ID1#
1
2
RIGHT
41
STAC9750_TQFP48
CD_AGND
LEFT
36
39
BIT_CLK
22 0.1U_0402_16V4Z MIC2 13 0.033U_0402_16V4ZPHONE
<19,29> IAC_RST#
+3VCC
<21>
35
2
1
2
LIN_IN_R
1
R365 4.7K_0402_5%
VCC
LINE_OUT_R
<28>
2
MD_SPK
CD_L_R
1 0_0603_5% 1 0_0603_5% 1 @6.8K_0603_1% 1 @6.8K_0603_1% 1 @51K_0402_5% 1 0_0402_5%
LINE_OUT_L
AUX_R
<28>
RIGHT
1
3
<29>
2 R360 2 R363 2 R362 2 R361 2 R369 2 R368 2
AUX_L
LEFT
1
<21> INT_CD_R
2
<21> INT_CD_L
0.1U_0402_16V4Z
2
15
VCC
AVCC 14
2 C544
38
U24
C477 0.1U_0402_16V4Z
AVCC
25
2
*
1 1 0 0
1 0 1 0
14.318 OPEN 27MHZ 48MHZ 24.576MHZ
4
Dell-Compal Confidential Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
E
F
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003 G
Sheet
27 H
of
47
B
C
D
* 1
U28
2
C570 10U_1206_10V4Z
R383 @10K_0402_5%
C583 0.1U_0402_16V4Z
2
INPUT IMPEDANCE
0
0
6dB
90K ohm
0
1
10dB
70K ohm
1
0
15.6dB
45K ohm
1
1
21.6dB
25K ohm
1
R384 10K_0402_5%
2
C582 0.1U_0402_16V4Z
1
2
2
16 15 6
2
1
AV(inv)
VDD PVDD1 PVDD2
C571 0.1U_0402_16V4Z
1
1
GAIN1
W=40mils 1
R380 @10K_0402_5%
GAIN1
2
GAIN0
2
+5VAMP
1
R379 10K_0402_5%
1 2 +5VALW L31 BLM21A05 _0805 1 2 +5VDDA L32 @BLM21A05_0805
GAIN0
1
Gain Setting
1
+5VDDA
E
Speaker Connector GAIN0 GAIN1
RIGHT
RIGHT
2 C584 17 0.1U_0402_16V4Z
1
RINROUT+
1
LIN+
1
2 C576 0.1U_0402_16V4Z
LIN-
LOUT+ <27>
LEFT
LEFT
5
GAIN1
18
INTSPK_R+
14
INTSPK_R-
4
INTSPK_L+
8
INTSPK_L-
JP16 INTSPK_R+ INTSPK_RINTSPK_L+ INTSPK_L-
1 2 3 4
15 mils trace
ROUT-
2 C581 9 0.47U_0603_16V4Z
3
D45 @DAN217_SOT23
LOUT-
1 2 3 4 ACES_85205-0400
@DAN217_SOT23 D43
1
<27>
GAIN0
1
RIN+
2
1
2 C579 7 0.47U_0603_16V4Z
1
1
A
R389 100K_0402_5% 2
1
GND1 GND2 GND3 GND4 2 G
TI6017A2_TSSOP20
1
C588 0.47U_0805_16V7K 2 2
1
3
2
3
2
1
R328 R157 @2K_0402_5% 2K_0402_5%
2
C161 4.7U_0805_10V4Z
EXT. MIC
MUTE
JP11
2
2
<30>
3
2
R327 1K_0402_5%
Q32 2N7002_SOT23
S
D42 @DAN217_SOT23
+5VDDA C580 @0.1U_0402_16V4Z
1
Q31 2N7002_SOT23
3
S
D 20 13 11 1
HP_PLUG
3
S
1
D
2 G
2
D44 @DAN217_SOT23
1
1 1
1
D
2 G
EAPD
3
<27>
2
BYPASS
10
BYPASS SHUTDOWN
<27> SPK_SHUTDOWN#
Q30 2N7002_SOT23
+3VS
12
NC 19
3
2
2
+3VS
5 L14 BLM11A121SPT_0603 1 2 <27>
MICIN
2
4 3 6 2 1
1 2 EXTMIC L29 BLM11A121SPT_0603
1
C548 0.22U_0603_10V7K
7 8
1 C458 47P_0402_50V8J
JA6333L-6S0-TR
2
1
+3VS
3
+3VS C621 0.1U_0402_16V4Z 1 2
IN1
O
4
IN2
3
2
2
SN74AHC1G08HDCK_TSSOP5
1
3
1
+5VDDA
NC VCC A Y
R436 100K_0402_5%
5
R437 100K_0402_5%
+3VS
4
GND
1
2
1
2
1
1
2
BEEP
R430 10K_0402_5% 1 2
G
<30>
+5VDDA
U15 U14
P
5
2
+3VS
1
R431 100K_0402_5%
C619 1 2
2
3
2
R125 100K_0402_5%
TC7SH14FU_SSOP5
+3V POWER 1
C620 1 2
C
<19>
ICH_SPKR
2
1
2
2 B
E
1 R432 2K_0402_5%
2
1
3
C623 1U_0603_10V4Z
MONO_IN
MONO_IN <27>
1U_0603_10V4Z
<27> HP_OUT_R
Q13 2SC2411K_SOT23
<27>
HP_OUT_L
R122 0_0402_5% 1 1 R155 0_0402_5%
@220U_D_6.3M_R40 C142 1 2 PR_RIGHT
2
1
2
PR_LEFT
C154 @220U_D_6.3M_R40
5
L12 BLM11A121SPT_0603 1 2
4
PR PL
1 2 L13 BLM11A121SPT_0603 1 1
2
C144 JA6333L-6S0-TR
C636 C622 1U_0603_10V4Z
1
3 6 2 1 7 8
C155 47P_0402_50V8J 2
2
JP9
1
HP_PLUG
HP_PLUG
2
2 47P_0402_50V8J
1
<23,25> PCM_SPK#
1 R433 2K_0402_5%
HP OUT <31>
+
2
@0.1U_0402_16V4Z
C624 1U_0603_10V4Z
+
R434 2K_0402_5%
+
C617 0.1U_0402_16V4Z
220U_10V_M 4
D15 1SS355_SOD323
1
+
4
2
2
C635 220U_10V_M
Dell-Compal Confidential Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
28
of
47
5
4
3
2
1
+3V
1 1 R443 1 R444
+3V +3VALW
2 0_0805_5% 2 @0_0805_5%
1 @1000P_0402_50V7K C627
2 1
C630 4.7U_0805_10V4Z
2
D
+5VMDC
1
+3VMDC @1000P_0402_50V7K C628 C625 @0.1U_0402_16V4Z
2
1 2
C626 @0.1U_0402_16V4Z
1
2
+5VALW
R435 @0_0805_5%
2
JP25
2 C629 0.1U_0402_16V4Z
1
<27>
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
MD_MIC
As close to P17
+3VMDC <19,27> IAC_SDATAO <19,27> IAC_RST#
MONO_OUT/PC_BEEP AUDIO_PWDN AGND MONO_PHONE AUXA_RIGHT RESERVED AUXA_LEFT GND CD_GND +5V CD_RIGHT RESERVED CD_LEFT RESERVED GND PRIMARY_DN 3.3Vaux RESERVED GND RESERVED 3.3Vmain AC97_SYNC AC97_SDATA_OUT AC97_SDATA_IN1 AC97_RESET# AC97_SDATA_IN0 GND GND AC97_MSTRCLK AC97_BITCLK
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
MD_SPK <27>
1 R438
2 10K_0402_5% +3V
D
1: Have primary CODEC on mother board IAC_SYNC <19,27> IAC_SDATA_IN1 <19>
R439 1 @22_0402_5% 2 1 R441 10_0402_5% 1 2 R442 22_0402_5% 2
IAC_BITCLK <19,27>
FOX_QT8A0301-3011
MDC Conn.
MDC Note Pin 1 is NC for Pctel and connexant MDC modem
Touch Pad & Status LED Conn. C
C
Pin 2 is NC for Pctel and connexant MDC modem JP13 <30>
TP_CLK
TP_CLK
1 3 5 7 9 11 13 15 17 19
+5VS
<21> ACT_LED# <31> CHARGE_LED#
ACT_LED# CHARGE_LED# +3VALW
TP_DATA
2 4 6 8 10 12 14 16 18 20
TP_DATA <30>
+5VS +5VALW PWR_LED# <31> BATT_LED# <31>
PWR_LED# BATT_LED#
Screw Hole
LID_SW# <30>
H7 H8 H13 H12 H3 H19 H11 H5 H4 H2 H10 H16 @C315D126 @C315D126 @C315D126 @C315D126 @C394D118 @C394D118 @C394D118 @C315D118 @C394D118 @C394D118 @C394D118 @C394D118
1 1
H34 @C177D87
H37 @C177D79
1
1 H6 @C315D177
1
H29 @O197x138D197x138N
1
1
1
1
1
1
1
1
1
1
1
H14 H17 H20 H21 H28 H27 H26 H18 @C315D118 @C315D118 @C315D118 @C315D118 @C315D118 @C315D118 @C315D118 @C138D138N
1
TP_DATA @220P_0603_50V8J
1
2
1
1 C171
1
TP_CLK @220P_0603_50V8J
1
2
1
1 C193
1
1
ACES 87216-2012_20P
CP1 4 CHARGE_LED# 3 ACT_LED# 2 PWR_LED# 1 BATT_LED#
5 6 7 8
B
H33 H30 H32 H15 H25 @O335x79D315x59@O335x79D315x59@O335x79D315x59@O335x79D315x59@H_O177x99D157x79
H9 @O335x79D315x59
H23 C197B256D157
H22 C197B256D157
H1 C256D87 B
1
1
1
1
1
1
1
1
1
@220P_1206_8P4C_50V8K
Fiduial Mark FD1
FD2
1
1
FD3 1
FD4 1
FD5
FD6
1
1
FD7 1
@FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK
FD8
FD9
1
1
FD10 1
FD11 1
FD12
FD13
1
1
FD14 1
@FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK A
A
FD15
FD16
1
1
FD17 1
FD18 1
Dell-Compal Confidential
@FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK @FIDUCIAL MARK
Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5
4
3
2
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet 1
29
of
47
1
+3VALW
C594 0.1U_0402_16V4Z
EC_AVCC
1
1
<19> LFRAME# <19> LAD0 <19> LAD1 <19> LAD2 <19> LAD3 <15> CLK_PCI_LPC 1 +3VALW R402
C593 1000P_0402_50V7K
2
CLK_PCI_LPC EC_RST 2 10K_0402_5%
1 2 ECAGND L34 BLM18PG600SN1_0603
AD B[0..7]
ADB[0..7] <31>
KBA[0..19]
<19>
SCI#
<18> <18>
GATEA20 KBRST#
<31>
+3VALW
1 R407
2 10K_0402_5%
TP_DATA
1 R404
2 10K_0402_5%
TP_CLK
2 R410
LID_SW# 1 100K_0402_5%
5 6 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7
KSO[0..15]
KSO[0..15]
Place closely pin 18 CLK_PCI_LPC
1
KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15
R406 10_0402_5%
1
2
C597 15P_0402_50V8J
2 +5VS RP7 PS2_CLK PS2_DATA KBD_DATA KBD_CLK
1 2 3 4
8 7 6 5
EC_TINIT# EC_TCK EC_TDO EC_TDI EC_TMS
8.2K_8P4R_1206_5%
+3VALW
KBD_CLK KBD_DATA PS2_CLK PS2_DATA TP_CLK TP_DATA LID_SW#
RP6 FSEL# SELIO# FR D# EC_SMI#
1 2 3 4
8 7 6 5
<29> TP_CLK <29> TP_DATA <29> LID_SW# <39> AC_LOW_PRES#
8.2K_8P4R_1206_5%
R423 1
20M_0603_5% 2 2
1 C615 10P_0402_50V8K
X5
2
1
<16>
2
RSMRST#
R395 100K_0402_5%
1
<33,38> SYSON <16,27,33,38> SUSP# <33,40> VR_ON <19,40> VGATE
1 0_0402_5%
2
R417 100K_0402_5%
<28>
MUTE
<16>
BKOFF#
<31>
CPU_DT/MO#
FSEL#
FSEL#
1
CPU_DT/MO#
EC_SMI# LAN_DISABLE#
<19> EC_SMI# <22> LAN_DISABLE# 1 0_0402_5% <19> EC_SWI# <26> RADIO_DISABLE# <15,19> PM_SLP_S1#
2 R390
G_RST#
R415
1
160
161
PORTC
IOPD0/RI1/EXWINT20 IOPD1/RI2/EXWINT21 IOPD2/EXWINT24/RESET2
PORTD-1
TINT# TCK TDO TDI TMS
JTAG debug port
PSCLK1/IOPF0 PSDAT1/IOPF1 PSCLK2/IOPF2 PSDAT2/IOPF3 PSCLK3/IOPF4 PSDAT3/IOPF5 PSCLK4/IOPF6 PSDAT4/IOPF7
PS2 interface
IOPE4/SWIN IOPE5/EXWINT40 IOPE6/LPCPD/EXWIN45 IOPE7/CLKRUN/EXWINT46
PORTE
IOPH0/A0/ENV0 IOPH1/A1/ENV1 IOPH2/A2/BADDR0 IOPH3/A3/BADDR1 IOPH4/A4/TRIS IOPH5/A5/SHBM IOPH6/A6 IOPH7/A7
PORTH
PORTI
IOPI0/D0 IOPI1/D1 IOPI2/D2 IOPI3/D3 IOPI4/D4 IOPI5/D5 IOPI6/D6 IOPI7/D7
PORTJ-1
IOPJ0/RD IOPJ1/WR0
32KX1/32KCLKIN 32KX2
SELIO#
+3VALW
2
158
C R Y2
IOPC0 IOPC1/SCL2 IOPC2/SDA2 IOPC3/TA1 IOPC4/TB1/EXWINT22 IOPC5/TA2 IOPC6/TB2/EXWINT23 IOPC7/CLKOUT
C618 12P_0402_50V8J
2
<19>
110 111 114 115 116 117 118 119
C R Y1
PORTB
KBSOUT0 KBSOUT1 KBSOUT2 KBSOUT3 KBSOUT4 KBSOUT5 KBSOUT6 KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12 KBSOUT13 KBSOUT14 KBSOUT15
105 106 107 108 109
IOPB0/URXD IOPB1/UTXD IOPB2/USCLK IOPB3/SCL1 IOPB4/SDA1 IOPB7/RING/PFAIL/RESET2
Key matrix scan
R424 1 120K_0402_5%
32.768KHZ_12.5P 3
49 50 51 52 53 56 57 58 59 60 61 64 65 66 67 68
IOPA0/PWM0 IOPA1/PWM1 IOPA2/PWM2 IOPA3/PWM3 IOPA4/PWM4 IOPA5/PWM5 IOPA6/PWM6 IOPA7/PWM7
PWM or PORTA
KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7
62 63 69 70 75 76
IOPJ2/BST0 IOPJ3/BST1 IOPJ4/BST2 IOPJ5/PFS IOPJ6/PLI IOPJ7/BRKL_RSTO
148 149 155 156 3 4 27 28
IOPM0/D8 IOPM1/D9 IOPM2/D10 IOPM3/D11 IOPM4/D12 IOPM5/D13 IOPM6/D14 IOPM7/D15
173 174 47
PORTD-2 PORTJ-2
PORTK PORTM
PORTL
SEL0# SEL1# CLK
IOPD4 IOPD5 IOPD6 IOPD7 IOPK0/A8 IOPK1/A9 IOPK2/A10 IOPK3/A11 IOPK4/A12 IOPK5/A13_BE0 IOPK6/A14_BE1 IOPK7/A15_CBRD IOPL0/A16 IOPL1/A17 IOPL2/A18 IOPL3/A19 IOPL4/WR1#
2
+3VALW
+3VALW
BATT_TEMP
BATT_CHGI B D_ID
0.3 100K/25K
1.0 100K/43K
<35,37>
EN_FAN2 EN_FAN1 IREF IREF2
<7> <7> <35> <35>
BEEP
<28>
B
4 5
1
3
FWR#
R394 43K_0603_1%
KSO16 KSO17 EC_DEBUG SMB_EC_CK1 SMB_EC_DA1
SMB_EC_CK2 SMB_EC_DA2
KSO16
2
1
C592 0.1U_0402_10V6K
<32>
SMB_EC_CK1 <16,31,34> SMB_EC_DA1 <16,31,34> PCIRST# <6,10,16,18,22,23,25,26,33> PWRBTN# <19> SMB_EC_CK2 <6,8> SMB_EC_DA2 <6,8> FAN1_TACH <7> EC_WAKEUP# <18> EC_THRM# <19> FAN2_TACH <7> PM_PWROK <10,19,32>
2
ACIN <18,34,36> PM_SLP_S4# <19> PM_SLP_S3# <15,19>
2 44 24 25
*
ON/OFF <32> PM_SLP_S5# <19> EXTVGA_IN# <16> CLKRUN# <19,22,25,26>
124 125 126 127 128 131 132 133
KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7
138 139 140 141 144 145 146 147
ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7
150 151
FR D# FWR# SELIO#
41 42 54 55 KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15
113 112 104 103 48
KBA16 KBA17 KBA18 KBA19
ENV1
TRIS
IRE
0
0
0
OBD
0
1
0
DEV
1
0
0
PROG
1
1
0
+3VALW
FRD#
SELIO#
KBA1
(ENV1)
2 R412
1 10K_0402_5%
KBA2
(BADDR0)
2 R414
1 10K_0402_5%
KBA3
(BADDR1)
2 R416
1 @10K_0402_5%
KBA5
(SHBM)
2 R418
1 10K_0402_5%
<31>
3
<31>
SCRLED# <32> NUMLED# <32> CAPSLED# <32>
143 142 135 134 130 129 121 120
ENV0
SHBM=1: Enable shared memory with host BIOS TRIS=1: While in IRE and OBD, float all the signals for clip-on ISE use
+3VALW JP17
FSTCHG
<35>
EC_TINIT# EC_TCK EC_TDO EC_TDI EC_TMS KSO16 KSO17 EC_DEBUG
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10
For EC debug BATT_CHGI BATT_TEMP
BATT-OVP
C591 1 1 C587
C585 1
2 2
2
0.01U_0402_25V4Z ECAGND
0.01U_0402_25V4Z
0.01U_0402_25V4Z ECAGND
@96212-1011S
ECAGND
1 C586
2
4
0.01U_0402_25V4Z
PC87591L-VPCN01 A2_LQFP176
Dell-Compal Confidential EC_FLASH# <19>
Q35 2N7002_SOT23
U33B SN74LVC32APWLE_TSSOP14
Title
Compal Electronics, Inc. SCHEMATIC, M/B LA-1452
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 星期五, 四月 25, 2003
R ev 1B
401230
A
B
C
1
ACOFF <35> VLBA# <19> EC_ON <32> LID_OUT# <19> PCM_SUSP# <23,24,25>
26 29 30
152
ADP_I
I/O Address Index Data BADDR1-0 2E 2F 0 0 4E 4F * 01 10 (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1 Reserved 1 1
2 G
A
O
S
6
1.5V
ECAGND
32 33 36 37 38 39 40 43
168 169 170 171 172 175 176 1
R393 100K_0603_1%
BATT-OVP <35> ALI/MH#
99 100 101 102
153 154 162 163 164 165
BATT_TEMP <34>
VBATT
1 FWE#
D
FWE#
P <31>
MOBILE
G
LOW
DT
7
HIGH
R421 100K_0402_5%
14
CPU
1
CPU_DT/MO#
R422 3.3K_0402_5%
0.2
VBATT
SUS_STAT# <16,19>
2
4
81 82 83 84 87 88 89 90 93 94
11 12 20 21 85 86 91 92 97 98
+3VALW
96
17 35 46 122 159 167 137
2
GND1 GND2 GND3 GND4 GND5 GND6 GND7
R396 @100K_0402_5%
0.1
1.0V
/10K 100K/10K
DA0 DA1 DA2 DA3
DA output
GA20/IOPB5 KBRST/IOPB6
71 72 73 74 77 78 79 80
REV
AD0 AD1 AD2 AD3 IOPE0AD4 IOPE1/AD5 IOPE2/AD6 IOPE3/AD7 DP/AD8 DN/AD9
AD Input
IOPD3/ECSCI#
0.5V
0V
+5VALW
Host interface
KSI[0..7]
2
+5VS
SERIRQ LDRQ# LFRAME# LAD0 LAD1 LAD2 LAD3 LCLK RESET1# SMI# PWUREQ#
31
<31,32> KSI[0..7]
KBA[0..19] <31>
7 8 9 15 14 13 10 18 19 22 23
BD_ID
C608 1U_0603_10V4Z
1
<18,23,25> SIRQ BLM18PG600SN1_0603 L33 1 2 2
1
2
2
0.1U_0402_16V4Z
95
U32
34 45 123 136 157 166
C602 0.1U_0402_16V4Z
1
2
2
1
E
+RTCVCC
VBAT
2
EC_3VDD
2 0_0402_5%
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10
2
1 R411
C589 1000P_0402_50V7K
AGND
2
C595
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6
C607
D
AVCC
0.1U_0402_10V6K 1 1
1
16
1
C611 4.7U_0805_10V4Z
C
EC_AVCC
VDD
+3VALW
B
+3VALW +3VS
2
A
D
Sheet E
30
of
47
A
<30>
ADB[0..7]
<30>
KBA[0..19]
B
C
D
E
AD B[0..7] KBA[0..19]
Output Port
Input Port
+5VALW
SELIO#
SELIO#
13
A B
0.1U_0402_16V4Z
KBA2
9
SELIO#
10
A
10
U33C O
B
8
LARST#
11 1
AA
CP MR
SN74LVC32APWLE_TSSOP14
2
C575 0.1U_0402_16V4Z
20
D0 D1 D2 D3 D4 D5 D6 D7
VCC
2
14
1 C605
GND
ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7
3 4 7 8 13 14 17 18
P
18 16 14 12 9 7 5 3
1
2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
PWR_LED# <29> CHARGE_LED# <29> BATT_LED# <29> VCHG <35>
SN74HCT273PW_TSSOP20
SN74LVC244APWR_TSSOP20 +5VALW
U33D O
7
<30>
12
P
KBA1
G
14
+3VALW
1G 2G
1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7
10
1 19
U27
+3VALW
G
PME#
<28> HP_PLUG <16> ENABKL <39> AC_LOW_PRES2# <34> 9C/12C#/8C#
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
0.1U_0402_16V4Z
7
2 4 6 8 11 13 15 17
2
20
U30 <16,17> M_SEN# <6,19> PROCHOT# <16> INTVGA_IN#
1
1 C577
VCC
+3VALW
1
+3VALW
2 100K_0402_5% 2 100K_0402_5% 2 100K_0402_5%
GND
1 R386 1 R233 1 R382
+3VS
1 R377
2 1 20K_0402_5%
2 C569 1U_0603_10V4Z
11 C C
NM24C164 Address definition: 1 A2 A1# A0 B2 B1 B0 R/W#
SN74LVC32APWLE_TSSOP14
+5VALW
1
+5VALW
+3VALW
1 2 <22>
LAN_PME#
1 R49 1 R48 1 R45
MINI_PME#
<26> MINI_PME#
PCM_PME#
<23,25> PCM_PME#
U29 8 7 6 5
+5VALW R387 10K_0402_5%
LAN_PME#
R375 100K_0402_5%
2
C590 0.1U_0402_16V4Z
+3VALW
2 0_0402_5% 2 0_0402_5% 2 0_0402_5%
AA
1 R419
2 100K_0402_5%
CC
1 R420
2 100K_0402_5%
1 R453 1 R454
<16,30,34> SMB_EC_CK1 <16,30,34> SMB_EC_DA1
2 SMB_EC_DA1 8.2K_0402_5% 2 SMB_EC_CK1 8.2K_0402_5%
2
2
1
2
VCC WP SCL SDA
A0 A1 A2 GND
1 2 3 4
AT24C16_SO8
EC I2C Bus Address: 24C164: 1011xxx R/W# 24C16: 1010xxx R/W#
PME#
CP2 KSI1 KSI7 KSI6 KSO9
5 6 7 8
@100P_1206_8P4C_50V8K CP3 KSI4 4 5 KSI5 3 6 KSO0 2 7 KSI2 1 8
INT_KBD CONN.
3
4 3 2 1
+3VALW KBA0 KBA1 KBA2 KBA3 KBA4 KBA5 KBA6 KBA7 KBA8 KBA9 KBA10 KBA11 KBA12 KBA13 KBA14 KBA15 KBA16 KBA17 KBA18 KBA19
@100P_1206_8P4C_50V8K CP4 KSI3 4 5 KSO5 3 6 KSO1 2 7 KSI0 1 8
1
3
5
7
9
11
13
15
17
19
21
25
2
4
6
8
10
12
14
16
18
20
22
24
Dummy 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
23
KSI1
KSI6
KSI4
KSO0
KSI3
KSO1
KSO2
KSO7
KSO6
KSO12
KSO14
KSO10
JP10
KSI7
KSO9
KSI5
KSI2
KSO5
KSI0
KSO4
KSO8
KSO3
KSO13
KSO11
KSO15
FOX_GS22250-0001
U16
<30> KBA[0..19]
@100P_1206_8P4C_50V8K CP5 KSO2 4 5 KSO4 3 6 KSO7 2 7 KSO8 1 8 @100P_1206_8P4C_50V8K CP6 KSO6 4 5 KSO3 3 6 KSO12 2 7 KSO13 1 8
<30> FSEL# <30> FRD# <30> FWE#
@100P_1206_8P4C_50V8K CP7 KSO14 4 5 KSO11 3 6 KSO10 2 7 KSO15 1 8
21 20 19 18 17 16 15 14 8 7 36 6 5 4 3 2 1 40 13 37 22 24 9
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
VCC0 VCC1 D0 D1 D2 D3 D4 D5 D6 D7
3
31 30 25 26 27 28 32 33 34 35
ADB0 ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7
1
1
2
C632 0.1U_0402_16V4Z 2
C631 0.1U_0402_16V4Z
ADB[0..7] <30> RP# NC READY/BUSY# NC0 NC1
CE# OE# WE#
GND0 GND1
10 11 12 29 38
1 R440
2 100K_0402_5%
+3VALW
23 39
SST39VF080-70_TSOP40
@100P_1206_8P4C_50V8K 4
4
<30>
KSO[0..15]
<30,32> KSI[0..7]
KSO[0..15]
Dell-Compal Confidential
KSI[0..7]
Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
31
of
47
A
B
C
D
E
1
+3VALW
R186 100K_0402_5%
RTC Battery BATT1
1
1 R448
S
1 3
S
1
1
2
2
<30>
BAS40-04_SOT23
EC_ON
EC_ON
1
1 2 R189 22K_0402_5%
CHGRTC
<37>
22K
2
1
D16 RLZ20A_LL34
2
2
+RTCVCC
2 +RTCVCC 470K_0402_5%
<30>
EC_ON#
1 1000P_0402_50V7K C209
22K Q21 DTC124EK_SOT23
3
2 1 3
2
D
1SS355_SOD323 1
3
2
1 1
100K
100K
D
SM_INTRUDER# <18>
C633 0.1U_0402_16V4Z
Q41 2N7002_SOT23
Q22 DTC115EKA_SOT23
WHEN R=0,Vbe=1.35V WHEN R=33K,Vbe=0.8V
SHDN_1632 <36>
Q40 2N7002_SOT23
2 G
SHDN#
D17 2
ON/OFF
DAN202U_SC70
R188 4.7K_0402_5%
3 2 G
<36>
D41
C639
2 R449 470K_0402_5%
R447 100K_0402_5%
2
1
ML1220T13RE
2 VL
3
RTCPWR +3VALW
VL
ON/OFF
1 ON/OFFBTN#
Power BTN
2
1
1
@1000P_0402_50V7K
+
2
1
-
1 C638 @1000P_0402_50V7K
1
2
D12
PM_PWROK <10,19,30>
2
2
USB PORT
USB Over Current 1
USB_AS USB_BS +3VALW
1
+5VALW
R212 100K_0402_5%
R12
W=40mils
USB_A
2
2
USB_AS
USB_BS
USB_B
U6
2
C16 0.1U_0402_16V4Z
100K_0402_5%
OVCUR#0
1 R211
2 47K_0402_5% 1
OVCUR#2
OVCUR#0 <19>
1
OVCUR#2 <19>
TPS2042ADR_SO8 C238 0.1U_0402_16V4Z
1 2 L38 FBM-11-451616-800T
1
2
2
1 1
+
+ C641 @100U_4A_10V
C10 2
C237 0.1U_0402_16V4Z
2
1 C12 0.1U_0402_16V4Z
+ C229
2
150U_D3_10VM
2
C642 @100U_4A_10V
150U_D3_10VM 0.1U_0402_16V4Z
N ote:
JP4
USB_AS=USB_BS=Trace width=40mils <33>
+ C231
2 1 L40 FBM-11-451616-800T
1
OC1# OUT1 OUT2 OC2#
2 47K_0402_5%
1
GND IN EN1# EN2#
1 R210
2
1
8 7 6 5
2
1 2 3 4
1 2 3 4
USB0DUSB0D+
SYSON#
3
1 C232 @15P_0402_50V8J
10 12
1 C11
2
VCC VCC D0- D1D0+ D1+ VSS VSS G2 G4
G1 G3
5 6 7 8 9 11
FOX_UB11123-8Z4-HT
2
USB2DUSB2D+
1
3
1 C13
2
2
C230 @15P_0402_50V8J
@15P_0402_50V8J @15P_0402_50V8J
JP5 <30> <30>
KSO16 CAPSLED#
+3VS
1 3 5 7 9
1 3 5 7 9
2 4 6 8 10
2 4 6 8 10
ON/OFFBTN#
KSI0 <30,31> SCRLED# <30> NUMLED# <30>
2 R209
1 0_0402_5%
2 R9
U21
+3VALW <19>
USBP0-
USBP0-
1
1 0_0402_5%
U17 4
USB0D-
USB2D-
USB0D+
USB2D+
4
USBP2-
1
USBP2-
<19>
USBP2+
<19>
SUYIN_12750AR-10G2T-9 <19>
USBP0+
USBP0+
2
3
3
@JTS0402-02_4P 1 0_0402_5%
2 R8
U22
3
6
2
3
4
5
Power SW Function Button
1
2
1
4
2
@JTS0402-02_4P
5
2 R208
USBP2+
1 0_0402_5%
@CM1210_6P 4
+3VS
Dell-Compal Confidential Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
32
of
47
A
B
C
D
E
+12VALW
1
+1.5VALW to +1.5VS Transfer +12VALW
R445 68K_0402_5%
1 +1.5VS
R451 100K_0402_5%
2
+1.5VALW
2
SUSON
D
S
1 2
<30,38>
C634 0.01U_0402_25V4Z
SUSP
3
S
3
Q60 2N7002_SOT23
RU NON
1
Q2 2N7002_SOT23
Q61 @SM05_SOT23
R450 1M_0402_5%
S
R446 47K_0402_5%
D
2 G
SYSON
2
SYSON# 2 G Q39 2N7002_SOT23 2 G
SYSON#
SYSON#
3
2
<32>
1
D
1
2
C572
1
C573 10U_1206_10V4Z
R378 470_0805_5%
2
SI4800DY_SO8
1
1
1 1
2
2
0.1U_0402_16V4Z
1 2 3 4
S S S G
3
C568 10U_1206_10V4Z
D D D D
1 2
1
1
1
U66 8 7 6 5
1
+12VALW
+CPU_CORE +3VALW
1
R426 10K_0402_5%
1 1 C208 2
<30,40>
2
VR_ON
1
2
S
Q36 2N7002_SOT23
S
2
R456 100K_0402_5%
D
VR_ON 2 G
Q37 @2N7002_SOT23
S
1
3
C207 22U_1206_10V4Z
R187 470_0402_5%
C210
1
1
SI4800DY_SO8
2
3
0.1U_0402_16V4Z
1 2 3 4
D
2 G
<16,27,30,38> SUSP#
2
1
S S S G
Q38 @2N7002_SOT23
2 G
2
2
D D D D
SUSP
3
U70 8 7 6 5
<7,17>
D 1
1
+3V
1
+3VALW
R425 @100K_0402_5%
2
2
R427 @330_0603_5%
+3VALW to +3V Transfer
D
22U_1206_10V4Z
SYSON# 2 G Q20 2N7002_SOT23
SUSON
3
S
+5VALW to +5VS Transfer +12VALW
R408 100K_0402_5%
1 1
R409
2 G
S
1
1 2 3 4
S S S G
1
SI4800DY_SO8 RU NON C601 0.01U_0402_25V4Z
2
2
3
R413 470_0805_5%
1 C603
2
C604 2
<18,22,23,25,26> C/BE#2 <18,22,23,25,26> AD8 <18,22,23,25,26> AD5 <18,22,23,25,26> AD1 <18,22,23,25,26> AD2 <18,22,23,25,26> AD6
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
PCI_TRDY# <18,22,23,25,26> PCIRST# <6,10,16,18,22,23,25,26,30> CLK_PCI_DEBUG <15> C/BE#3 <18,22,23,25,26> C/BE#1 <18,22,23,25,26> AD7 <18,22,23,25,26> AD3 <18,22,23,25,26> AD0 <18,22,23,25,26> AD4 <18,22,23,25,26> C/BE#0 <18,22,23,25,26>
C/BE#0
3
1@AMP 5-175638-0
1
Q33 2N7002_SOT23
D
0.1U_0402_16V4Z +5VALW
3
S 1
+
2 SUSP G Q34 2N7002_SOT23
Debug
C606 150U_D3_10VM
PORT
CLK_PCI_DEBUG
2
SUSP
D
D D D D
1
2
8 7 6 5
JP27 <18,22,23,25,26> AD9 <18,22,23,25,26> PCI_FRAME#
22U_1206_10V4Z
U31
1M_0402_5% 3
+5VS
2
1
+5VS +5VALW
R458 33_0402_5%
1
2
1 C637 10P_0402_50V8K
2 +3VS
+3VALW to +3VS Transfer
U20
1
+
C145 150U_D2_6.3VM
2
SI4800DY_SO8 C132 10U_1206_10V4Z
1
C131 0.1U_0402_16V4Z 1 R100 470_0402_5%
C133 2 22U_1206_10V4Z2
4
1
2
1
S S S G
D RU NON
S
3
4
D D D D
1 2 3 4
2
8 7 6 5
1
+3VALW
SUSP 2 G Q19 2N7002_SOT23
Dell-Compal Confidential Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
33
of
47
A
B
C
D
E
Detector
+3VALWP BATT+ PL4 LOW_PWR <39>
2
MBH2012102YZT_0805
PR161
BATT++
BATT+
1
1
1
100K_0402_5% PL5 BATT++
2
PL6
1 1 2
PCN2
MCK4532800YAT_1812
2
10 11
BATT+ BATT+ ID B/I TS SMD SMC GNDGND-
GND GND
PD6
1 2 3 4 5 6 7 8 9
@BAS40-04
PR47 1 PR46 1K_0402_5%
SUYIN-200275MR009G516ZL 9P
2
PC219 2 1
2
2
PR48 100_0402_5% 2
1
SMB_EC_DA1 <16,30,31>
PR49 100_0402_5% 2 1 <16,30,31> SMB_EC_CK1
PD7 @BAS40-04
PD8 @BAS40-04
2
3
1
S M ART Battery: 1 . B ATT+ 2 . B ATT+ 3 .9C/12C#/8C# 4 .B/I 5. TS 6 . S M B _EC_DA1 7 . SMB_EC_CK1 8 . G ND 9 . G ND
2
+3VALWP 25.5K_0402_1%
1
PCN2 battery connector pin assignment
BATT_TEMP <30>
3
PZD1 RLZ24B
PR45 1K_0402_5% BATT_TEMP 2
1
1
2
PC47 2 1
560P_0603_50V7K
PL7 ADPGND 1
1K_0402_5%
PR44 10_1206_5%
2
MCK4532800YAT_1812
PC48 12P_0603_50V8J 2 1
1 2
PC45
PC46 1 2
4 5 6 7
2
560P_0603_50V7K
GND AIR_ADP
12P_0603_50V8J
VIN 1
PR163 @1K_0402_5%
PC44 0.1U_0805_25V7K
PC43 0.1U_0805_25V7K
2
1
A DPIN 1
3
2200P_0603_50V7K
PCN1 RP34-8RD-3PDL2J
9C/12C#/8C# <31> PR162
1
VIN
2
1
1 2 FBM-L18-453215-900-LMA90T_1812
3
2
+5VALWP
VL
+5VALWP 2
1
2
PR51 2.2M_0603_5% 1 VS
B+
PC52 0.01U_0603_50V7K
PR52 499K_0603_1%
PR56 1M_0603_1% 2
4
LM393A
1
1 1 2
<18,30,36>
<35>
PR32
Precharge detector 15.97V/14.84V FOR ADAPTOR
PQ12 2N7002
66.5K_0603_1%
2
2
PR60 47K_0603_5% 1 P ACIN
PACIN
<35>
1
ACIN
PACIN
PR63 10K_0603_5%
100K
2
PQ13 DTC115EUA
2
PZD2 RLZ4.3B
+5VALWP
100K 4
3
2
PC54 0.1U_0603_16V
2 34K_0603_1%
1
PR58 7
1
PC49 1000P_0603_50V8J
1
1 1
+
6
1
5
2
PU5B
8
PR61 22K_0603_5% 1 2
PR59 10K_0603_5% 1 2
10K_0603_5%
VS
2
PR62 20K_0603_1% 2 1
PC53 1000P_0603_50V8J 2 1
PR57 84.5K_0603_1% 2 1
VL
4
4 PR54
VIN
VIN
PR53 499K_0603_1% PR55 191K_0603_1%
2
1
2
2
2
3
3
1
ACON
-
2
<35>
LM393A
3
1
PD10 RB751V
+
2
<6,36> SHDN_1632#
Vin Detector 17.90V/17.24V
1
PC51 1000P_0603_50V8J
1
PC50 0.1U_0603_16V 2 1
2
1
PD9 RB751V
3
8
PU5A
2
2
1
1
PR50 100K_0603_5%
2
1
RTCVREF
PR64 10K_0603_5%
Dell-Compal Confidential Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
34
of
47
A
B
C
D
Charger
Iadp=0~4.10A(90W) Iadp=0~3.20A(70W) Iair=0~2.25A(Air)
B+++
P3
PR68 150K_0402_5%
4
2200P_0603_50V7K
2
PC58
PC57 2 1
1 1
2
1
2
5 6
7
9
1 2
PR86 20K_0603_1%
2
1
10
CS
-INE2 VCC(o) FB2
OUT
VREF
VH
FB1
VCC
-INE1
RT
+INE1 OUTC1
-INE3 FB3
23
21
11
OUTD
CTL
-INC1
+INC1
2
1
2
100K
100K
PC60 0.1U_0805_25V7K
20 PC63 0.1U_0603_16V 1 2
19
1
18 1
17
16
ACON
2
PR85 1
ACOFF
<30>
PQ18 DTC115EUA
PC66 0.1U_0805_25V7K 2
2
1
PL9 15U_SPC-1204P-150 1 2
<34>
PR81 47K_0603_1%
15
2
LXCHRG
330K_0603_5%
PR84 10K_0603_5%
1
5 6 7 8
PC59 2200P_0603_50V7K CS
22
PC69 2
PR82 0.02_2512_1% 1 2
PD13 EA60QC04
1500P_0603_5%
14
BATT+ 2
BATT+
+
PC71 4.7U_1210_25V 2 1
PR76 2 1 2 10K_0603_5% PC62 4700P_0603_50V
1
+INE2
GND
PC70 4.7U_1210_25V 2 1
4
OUTC2
PC68 47U_EC_25V 2 1
3
3
PC61 1 2
0.01U_0402_16V
2
2
PR83 21K_0603_1%
IREF=0.82*Icharge IREF=0~3.3V
1 PR71 100K_0603_5%
PC65 PR79 2200P_0603_50V7K 1K_0603_5% 8
0.01U_0402_16V
1
IREF
10K_0603_5% ACOFF#
3
IREF2
2
<30>
VIN
PR70 PQ17 SI4835DY_SO-8
2
2
0.1U_0603_16V 2 1
PC64 1
1
<30>
+INC2
1
PR67 47K_0603_5% 2
1
4
1
1
PR73 16.9K_0603_1%
PR80 @30.1K_0603_1%
PQ19 2N7002
PC72 2 1
S
ACON
ACON
2
D
2 G
PR74 2 1 @28.7K_0603_1%
<34>
ADP_I
-INC2
24
PQ16 SI4825DY_SO-8 8 7 6 5
1
<30,37>
PR72 22K_0402_5% 2
PR75 21K_0603_1% 2 1
1
2
PACIN
3
<34>
PR69 0_0603_5%
PU6 MB3887 1
1 2 3
1 12
2 PR87 @10K_0603_5%
13 PC73 10P_0603_50V
+3VALWP
2
2
2
1
2
PD11 1SS355 ACOFF#
0.1U_0805_25V7K
1
1
3 2 1
2
4
PR66 200K_0402_5%
PC56 10U_1210_25V
+
2
1 2 FBM-L18-453215-900-LMA90T_1812
1
PL8
1
PC55 10U_1210_25V 2 1
2
1
PR65 0.02_2512_1%
8 7 6 5
PC226 @15U_D_25V
1 2 3
4
1
PQ15 SI4825DY_SO-8
1 2 3
1
8 7 6 5
B+
P2
PQ14 SI4825DY_SO-8 VIN
E
1
CS
2
1
PR231 47K_0603_5%
2
100K
PR164 104K_0603_0.1% 2 1
1
PQ63 DTC115EUA BATT++
3
-
2
3
2
Charge voltage 4S CC-CV MODE : 16.8V VCHG is H 4S PULSE MODE : 17.4V VCHG is L
PC74 22P_0603_50V
1
PR37 100K_0603_5% 2 1 +5VP PQ41
100K
DTC115EK 2 VCHG
<31>
100K 3
1 2
PR91
1
0.1U_0603_16V PC154
1 8 +
PC76
0.01U_0603_50V7K
2
PR93
1
PR92 @2.2K_0603_5% 2 1
PC75 4
@0.1U_0603_16V 2 1
LM358
PC119 0.01U_0603_50V7K 2 1
2 1 BATT-OVP
1
4
PU7A
845K_0603_1%
PR90
3
VS
PQ40 2N7002
300K_0603_0.5%
PQ64 DTC115EUA
100K
<30>
3
100K
FSTCHG
143K_0603_0.5%
2 <30>
1
PR89 312K_0603_0.1%
PR36 2.2M_0603_5% 2 1
2
3 3
2
100K
4
OVP voltage :
Dell-Compal Confidential
LI-4S :18.0V----BATT-OVP=2.00V
Compal Electronics, Inc. Title
LI-3S :13.5V----BATT-OVP=1.50V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date:
BATT-OVP=0.2206*BATT++ A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
35
of
47
A
B
C
D
E
+3.3V/+5V/+12V
2
B+
1
1
PL10
1
FBM-L11-322513-151LMAT
1
2 3
FLYBACK
2
3 1
PC86 0.1U_0603_16V
5 6 7 8
2
4
3 2 1
PC90 4.7U_1210_25V
PC89 4.7U_1210_25V 2 1
PC88 0.1U_0805_25V7K 2 1
PC87 2200P_0603_50V7K 2 1
1
1
DH51
2
5 6 7 8
1 2
PC93 0.1U_0805_25V7K
1 2
PR98 0_0402_5%
PC228 @15U_D_25V
+
2
1
2
2
PC85 4.7U_1206_10V
1
1 2
+12VALWP
PT1 9U_SDT-1204P-100-120
PQ22 SI4800DY_SO-8
CSL5
2
1
POK
1 PR114
2
@0.047U_0603_16V
+5V Ipeak = 6.66A ~ 10A
1
PR118 47K_0603_1%
PR120 100K_0603_1% VL
PR121 100K_0603_1%
SHDN#
<32>
200K_0603_1%
NC_TEST1
2 SHDN_1632 <32>
3
PC158
1
1
PC112
+
2
2
3
0.047U_0603_16V
PC114 1U_0805_25V
2
8
LM393A
0.47U_0603_16V 2 1
47K_0402_1% PU9A
PQ42 2N7002
1
PR116
VL PR119 19.1K_0603_1%
4
PR117
1.96K_0603_1%
1
2
2 PD18 @RB751V
2
1
PC111
PR178
PH1 10K_0603_1%
PC106 150U_D_6.3V_FP
PC110
@0_0603_5%
PR177 20K_0603_1%
VL
PC113 2 1
3
10K_0402_1%
VL
1000P_0603_50V8J
+
@100P_0402_50V8K
PR115
NC_TEST2
4
+
2
2
2
1
2 VL
PD17 EP10QY03
2
1 PR112 @100K_0402_5%
PR113 0_0402_5% SHDN_1632# <6,34>
PC108 100P_0402_50V
1
PR109 10.2K_0402_1%
2 PR108 0_0402_5%
2
1
2
2 PR107 @0_0402_5%
1
8
1
VL
680P_0402_50V
1
1
PC104
+5VP
PC105 150U_D_6.3V_FP
+5VALWP
2
PC103 4.7U_1206_10V +3VALWP
1 1
PR110 @0_0603_5%
PC109 @1000P_0402_50V7K
1 2
2.5VREF
2
PR111 10K_0402_5% 1 2
2
PD16 EP10QY03
3
PR103 0.012_2512_1%
2
VL
V+
RUN/ON3
2 1 3 2 1
PR102 2M_0402_5%
TIME/ON5
2
28
MAX1632
4
1
7
PR106 @300K_0402_5%
CSH3 CSL3 FB3 SKIP# SHDN#
PC96 47P_0402_50V CSH5
1
PC102 100P_0402_50V
LX3 DL3
DL5
1
1
1
2
PR104 10K_0402_5%
PU8
PQ24 SI4810DY_SO-8
1
1
<18,30,34> ACIN
1 2 3 10 23
DH3
4 5 18 16 17 19 20 14 13 12 15 9 6 11
12OUT VDD BST5 DH5 LX5 DL5 PGND CSH5 CSL5 FB5 SEQ REF SYNC RST#
2
CSH3
BST3
GND
26 24
2
PR105 3.57K_0603_1% 1 2
1 +
2
PC99
150U_D_6.3V_FP 2 1
PC98 150U_D_6.3V_FP 2 1
+
27
1M_0402_5%
PR101 0.012_2512_1%
2
+3VALWP
PR100 1
1
2
25
21
22
2
PR99 0_0402_5%
1
1 2 3
4
B++++
PC92 4.7U_1210_25V
DL3
1
PR96 1
PQ23 SI4810DY_SO-8
47P_0402_50V
1
PC91 0.1U_0805_25V7K
8 7 6 5
2
LX3
PR97 10_1206_5%
2
1 2 3
1
PR95 0_0402_5% 2
D H3
PL11 10U_SPC-1204P-100
PD14 EC11FS2
PC84 0.1U_0805_25V7K 1 2
VS
0_0402_5%
DH31
4
+3.3V Ipeak = 6.66A ~ 10A
PR94 22_1206_5% SNB 2 1
VL PQ21 SI4800DY_SO-8
PC94 2 1
2
BST51
4
8 7 6 5
PC227 @15U_D_25V
PC83 4.7U_1210_25V
PC82 4.7U_1210_25V 2 1
PC81 2200P_0603_50V7K 2 1
1
PC80 0.1U_0805_25V7K
2
+
DAP202U PD15 BST31
2
2
1
PC77 4.7U_1210_25V 2
1
PC79 0.1U_0805_25V7K B++++
PC78 470P_0805_100V 1 2
1
4
CPU thermal protection at 90 degree C Recovery at 45 degree C
Dell-Compal Confidential Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
36
of
47
A
B
C
D
E
+1.5VALW+-5% +1.5VALWP PQ26 SI3445DV
D
PL12 4.7U_SPC-1205P-4R7A
PC125 2 1
VL VS
1 PC236 0.01U_0603_50V7K
1
8
2
2
PR305 226K_0402_1%
1
3
2.5VREF
1
2
1
2
PR307 137K_0402_1%
PR306 100K_0402_1%
2
LM393A
3
-
2
3 PQ84 2N7002
+
1
1
4
2 G
PC239 0.01U_0603_50V7K
4
PU21A
D
PC238 0.022U_0402_16V 2 1
6
PR304 2M_0402_5% 1
1
2 2 G
PR133 301K_0603_1%
5
-
PR308 47K_0402_1%
PQ83 2N7002
PR131 200K_0603_1% 2 1
2
D
S
0.01U_0603_50V7K 2 1
+
2
PR303 47K_0402_1%
S
PC122 0.1U_0603_16V
1 7
1
2
8
2 PQ28 2SA1036K
1
VL
2 3
PU9B LM393A
1
H_PROCHOT#
1
1
PC116 150U_D_6.3V_KO
PC148 2 1
2
+ 470P_0603_50V 2
VL
PC121 2200P_0603_50V7K
PR122 10K_0603_5% 2 1
1 2
PR127 2
1
1
3
1 2PR125
2SC2411K
10K_0603_5%
PQ27
1
1K_0603_5% 2 2 PR126
3
1
PC147 0.1U_0603_16V
1
2 1
1 2
PC118 4.7U_1206_25V
G
1
PD19 RB751V
PD20 RB051L-40
S 4
+3VALW
LX18
6 5 2 1
1M_0603_5%
+5VALW
PD36 2
ADP_I
1
<30,35>
<6> H_PROCHOT# @RB751V
PU21B 2
2
Adaptor Current Detector ADP_I : 2.01V.... clock throttle(Iin=5.025A) ADP_I : 1.81V....No clock throttle(Iin=4.525A) 1
PR134 200_1206_5% 2
1
PR135 200_1206_5% 2
7
+
5
-
6
LM393A
PD21 RLS4148 1
2
VS1
PD22 RLS4148 1
2
1
2
1
3
1
1
PJP2 4MM
1.5K_1206_5%
PR33 1 2
1
1
1.5K_1206_5%
2
PR140 10K_0603_5% 2
PR138
PQ31 TP0610T
2
1
PR137
1 2
PR136
BATT+
1.5K_1206_5%
VS
PD23 RLS4148
2
VIN
1.5K_1206_5%
2
+2.5VP
+5VP
1
+5VALWP
IN
OUT GND 1
PR144 200_0603_5% 1 2
PR34 200_0603_5% 1 2
2
+12VALWP
1
+3VALW
2 +12VALW
PR124 0_0603_5%
6
1 3
4.7U_1206_25V
PC130 1U_0805_25V
2
PC129 2 1
CHGRTCP
1
2
2MM
5
PR123 2
RTCVREF
PU10 S-81233SG
2
+5VALW
PJP6
+
PU7B
1
2
1
LM358
-
2
3
2
7
4
+1.5VALW
PJP5 3MM
0_0603_5% 1
1
1
2
0.1U_0603_16V
PC128 2 1
PR142 1 2
150K_0603_5%
1 2
PC127 0.1U_0805_25V7K
0.22U_1206_25V
PC126 2 1
PR141 100K_0603_5% 2 1
PZD4 RLZ5.1B
PR143 22K_0603_5%
PZD5 RLZ16B
2
PJP4 3MM
+3VALWP EC_ON#
1
B+
3
<32>
+2.5V
2
PZD3 RLZ4.3B
2
PJP3 2MM +1.5VALWP
PR139 200_0805_5%
1
PJP8 3MM +1.25VP
CHGRTC
1
2
+1.25VS
4
Dell-Compal Confidential Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A
B
C
D
SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet E
37
of
47
5
4
3
2
1
+
PC229 @15U_D_25V
PL21 HCB4532K-800T90_9A 1 2
PC200 4.7U_1210_25V
PC199 4.7U_1210_25V
PC197 0.1U_0805_25V7K
1 2
PC198 4.7U_1210_25V
D
PC196 2200P_0603_50V7K
D
B+
PR278 51_1206_5% +5VALWP
+2.5V/+1.25V
2
3 SI4800DY_SO-8
2.2_0603_5%
PC201 2.2U_0805_10V
PD34
8 7 6 5 PQ79
DAP202U
1
PC202 0.1U_0805_25V7K
PR299
+2.5V Ipeak =8.49A ~ 14.78A
PR31 SUSP#
<16,27,30,33> +2.5VP
@1K_0402_5%
0_0603_5% 24
0_0603_5%
4
5
25
PR283
3
6
2
7
1
8
9 10 8 15 11 PR290 0_0603_5%
LGATE2
PGND1
PGND2
VOUT1 VSEN1 EN1 PG1
VOUT2 VSEN2 EN2 PG2/REF
OCSET1 IS6225
OCSET2
PR286 @100_0603_5%
2K_0603_5%
27
PC214 @1000P_0603_50V8J
26 20 19 21 16
2
22
+
PC212 4.7U_0805_10V4Z
SDREF
2
3
PL23 1.5U_TPR6D38-1R5M 1 2
PR285 ISEN2
LGATE1
2
+1.25VP
PC215
18
PC216 @1000P_0603_50V8J
4.7U_0805_6.3V6K
1
2
ISEN1
DDR
7 1K_0603_5%
1 2 3
PHASE2
ISL6225
PR284 SI4810DY_SO-8
PC217 @1000P_0603_50V8J
UGATE2
PU20
PHASE1
C
1
UGATE1
1
1 PQ81 FDS6984S
PC211
4
PC224 0.1U_0603_16V
220U_D_2V
PR282
13
1 PD35 2
5 0_0603_5%
PR289 10K_0603_1%
PR280
0.1U_0805_25V7K PQ80 4
GND
PR288 @0_0603_5%
BOOT2
1
18.2K_0603_1%
@1000P_0603_50V8J
PR287
0.01U_0603_50V7K
PC213
PC210
PR281 @100_0603_5%
0.01U_0805_50V7KPC207 0.1U_0805_25V7K 23
PR279
@EC31QS04
220U_D_4V_FP
PC208 2 1
1
+
2
PC209
220U_D_4V_FP
+
17
PC205 10U_1206_6.3V7K
0.01U_0603_50V7K 0_0603_5% 6 BOOT1
PC206
DDR Termination Voltage
PC204 SOFT2
2
PL22 4.7U_SPC-1205P-4R7A
+2.5VP
8 7 6 5
C
VCC
SOFT1
1 2 3
12
VIN
PC203
28
14
4
PR291 51K_0603_1%
B
B
+5VALWP
+2.5VP PR30 PR292 <30,33> SYSON
2
2
1
1 PR293 10K_0603_0.1%
SUSP#
<16,27,30,33>
0_0402_5%
0_0603_5%
1 PR296
1
1
SYSON <30,33>
@0_0402_5%
PR295 10K_0603_0.1%
2
10K_0603_5%
2
2
470P_0603_50V7K PC218
PR294
+3VALWP
+2.5VPGD
A
A
Dell-Compal Confidential Compal Electronics, Inc. Title
SCHEMATIC, M/B LA-1452
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS B 401230 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 星期五 , 四月 25, 2003 5
4
3
2
R ev 1B Sheet 1
38
of
47
5
4
3
2
1
AC Adapter Detector
D
D
AC Adapter
IREF2
LOW_PWR
AC_LOW_PRES#
AC_LOW_PRES2#
90W
0V
0
0
2.96V
70W
Float
0
1
2.31V
20V
1
1
1.62V
VIN
1
VIN
AIRLINE
PR170 10K_0603_5%
C
1 PR168 10K_0603_5%
2
1 2
VIN
PC155 0.01U_0603_50V7K
2
+5VALWP
C
8
PU14A LM393A
1
PC156
3
+
2
-
1 AC_LOW_PRES# <30>
4
2
@1000P_0603_50V8J
1
1
+5VALWP
1
PR171 10K_0603_5%
PR169 10K_0603_5%
2
PR173 10K_0603_5%
VIN
2
PR302 2
2
1 <34> LOW_PWR
8
PU14B
1
PC157
5
@1000P_0603_50V8J
6
+
7
AC_LOW_PRES2# <31>
-
2
4
2
PR174 10K_0603_5%
LM393A
1
10K_0603_5%
B
1
B
2
PR172 10K_0603_5%
A
A
Dell-Compal Confidential Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5
4
3
2
Compal Electronics, Inc. SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 星期五, 四月 25, 2003
Sheet 1
39
of
47
A
B
C
D
E
F
G
H
PL17 B+ FBM-L18-453215-900-LMA 90T_1812
CPU_B+
Different Pin Definition for ISL6215 in PU16 CPU_B+
1 0_0603_1% PQ71 DTC115EUA
100K
PR260
3
2
PR265 100K_0603_5%
PR266
PC165 47U_EC_25V
PC164 2200P_0603_50V7K 2 1
PC163 0.1U_0805_25V7K
PC162 @10U_1210_25V 2 1
PC161 @10U_1210_25V
3 2 1
1
2
1
2
5 6 7 8
1 2
3 2 1
3 2 1
1 1
PU17 6 3 7 4
2
0_0603_5%
VCC
BOOT
PWM
UGTE
EN
PHSE
GND
LGTE
2 1
1
2
4
4 PQ70 IR7811A
PL19 0.6U_HK-AE26A0R6
PR259 0_0603_5%
8 5
ISL6207
PC221 2200P_0603_50V7K
PR254
@5.1_0603_5%
+
PC220 0.1U_0805_25V7K
PR251
ISL6207_EN
+
IR7811A
PC176 10U_1210_25V 2 1
CPU_B+ PQ69
PQ72 SI4362DY_SO-8
2
4
+CPU_CORE
+CPU_CORE
PQ73 SI4362DY_SO-8 PR261 @5.1_0805_5%
PH7
4 PD31
0_0603_5% @EC31QS04
PC184 @1000P_0603_50V8J
1.43K_0603_1%
1
1
ISL6207_EN
3
GND
LGTE
1
2
PC223 2200P_0603_50V7K
PC222 0.1U_0805_25V7K
10U_1210_25V 2 1
PC189
PC188 10U_1210_25V
PC187 10U_1210_25V
PC186 10U_1210_25V
PC235 @15U_D_25V
PC234 @15U_D_25V
5 6 7 8
3 2 1
PL20 0.6U_HK-AE26A0R6
PR273 0_0603_5%
5
PD32
2
PHSE
1 8
+CPU_CORE
+CPU_CORE
1
EN
2
PR275 @5.1_0805_5%
PH8 ISL6207
@EC31QS04 0_0603_5%
1
4
1
4
PQ78 SI4362DY_SO-8
2
PQ77 SI4362DY_SO-8
2
PC193 1 2
1
4
UGTE
5 6 7 8
+5VALWP
BOOT
PWM
3 2 1
2
7
VCC
2
2
ISL6207_EN
PR301 100K_0603_5%
PC195 @1000P_0603_50V8J
PR276 1.5K_0603_1%
PR249 PR256 PR268 P C171
1
DE-POP
3
PQ76 IR7811A
+
3 2 1
CM2843
PR274 0_0603_5%
6
4
3 2 1
2
IR7811A 4
5 6 7 8
GND
0_0603_5%
PC191 1 2
1 EN
1
@5.1_0603_5% PU19
PR271 2
0.1U_0805_25V7K
PG
2
3
1
5
PC194 @0.01U_0603_50V7K
VOUT
499K_0603_1% PR277 2 1
4
+1.2VP
VIN
+
PR270
1U_0805_25V 1 2
1
2
PC190 4.7U_1206_16V
1.2VDD
PC192 4.7U_1206_16V
1
0_0603_5%
PQ75
2
3 PU18
PR268 1
2 0.1U_0603_16V
PR272
+5VS
PQ82 2N7002
5 6 7 8
CPU_B+ 2
@300K_0603_5%
3
1
PQ74 2N7002
PR267 1 2 @280K_0603_1%
2 PC185
VR_ON
5 6 7 8
+5VS
PR263
1 1 PR269 100K_0603_5%
3
<30,33>
DE-POP all items in dash- area if ISL6215is used for mobile CPU
10K_0603_5%
1
+3VALWP
PC181 1 2
100K +5VALWP
2
1
@10K_0603_1%
2
2
PR256 1
2
1
@3.24K_0603_1%
1U_0805_25V
1
1
PR258
1
@80.6K_0603_1%
PR252 90.9K_0603_1%
1 PR255
2
2
@10.2K_0603_1%
1.15K_0603_1% 1
CPU_B+
2
PR250
PR297 2
GND
2 PR253
FSET/EN
2
2
26 14
1.96K_0603_1%
2
NC
PR245
2
NC
PC178 1 2
1
1
13 @3.09K_0603_1% 7
15
PC170 @1000P_0603_50V8J
1
NC
4 PQ68 SI4362DY_SO-8
2
VSEN
NC
@0.1U_0603_16V
12 PR248
PD29 EC31QS04
4 PQ67 SI4362DY_SO-8
1
NC
2
PR247 @10K_0603_5%
16
@5.1_0805_5%
PH6 0_0603_5%
2
8
PR241
@EC31QS04
5 6 7 8
11
1
2
PR236 @0_0603_5%
9
+CPU_CORE
+CPU_CORE
3 2 1
NC
PD28
ISL6207
5 6 7 8
ISL6219
5
3 2 1
NC
10
PL18 0.6U_HK-AE26A0R6
3 2 1
FB
2
PR237 0_0603_5%
5 6 7 8
COMP
NC
LGTE
PC168 0.01U_0603_50V7K
NC
2
6
ISEN2
21 20
GND
1
1 8
3 2 1
<15,19> PM_STPCPU#
NC
19
PHSE
1
5 6 7 8
17
PWM2
UGTE
EN
4 PQ66 IR7811A
0.1U_0805_25V7K
27
ISEN3
PGOOD
BOOT
PWM
2
2
<19> PM_DPRSLPVR
VID4
18
1
5
25 0_0603_5% 24
PR246
23
1
2
<19,30> VGATE
PWM3
0_0603_5%
VCC
PC183 @0.01U_0603_50V7K
<6,8> CPU_VID4
0_0603_5% 1
ISEN1
VID3
2
PR243
VID2
4
1U_0805_25V 1 2 499K_0603_1% 2 1PR244
4
1 2 499K_0603_1% PR262
3
0_0603_5% 1
PC169 1 2
0_0603_5% 1
2
22
7
PC182 1U_0805_25V 1 2
2
PR242
PWM1
PC171 1 PR249 2 2 1 10K_0603_1% 15N_0603_50V7K 1 PR257 2 2 1 PC179 2 1 @909_0603_1% @5.6N_0603_50V7K 150P_0603_50V8J PC172
PR240
VID1
3 ISL6207_EN
1 PH5 2 1 PR298 2 4.7K_0603_3% 681_0603_1%
<6,8> CPU_VID3
2
28
1.74K_0603_1%
<6,8> CPU_VID2
20_0603_5%1
VCC
1
1 PR239
VID0
PC166 4.7U_1206_25V
1
<6,8> CPU_VID0 <6,8> CPU_VID1
2
PU16
0_0603_5% 2 1
PR238
PU15 6
2
3 2 1
1
1
PC167 1 2
SOFT
PR233
0.1U_0805_25V7K
2
PQ65 IR7811A 4
PR232 10K_0603_5%
PC180 1 2
#26
5 6 7 8
5 6 7 8
PR300 2.2_0603_5%
1
ALTEN
+
2
#27
PC175 10U_1210_25V
VRTN
PC160 10U_1210_25V
#15
+
PC174 10U_1210_25V
OCSET
+
PC159
#11
+5VS
10U_1210_25V
EN
PC173 10U_1210_25V
NODV
#24
2
#17
OFFSET
1
ALTV
#13
PC231 @15U_D_25V
#12
VMON
PC233 @15U_D_25V
RAMPS
#8
PC232 @15U_D_25V
#6
PC230 @15U_D_25V
+5VS
4
4
ISL6219 for desk-top
PR247, PR255, PR260 PR248, PR250,PR258, PC178,PC172,PR236
7.5K
PR266, PQ74, PQ71 PR253, PC179, PR257
6.04K 1.5K
1.74K unpop 5.6nF PTC solution
1.PH6,PH7,PH8 pop thermal resistor 2. Non-pop PR298 and PH5 3.PR297 0 ohm
Dell-Compal Confidential
Compal Electronics, Inc. ISL6215 for mobile
130K 4.7nF
NTC solution
1.PH6,PH7,PH8 pop 0 ohm resistor Title 2. Pop PR298 681_0603_1%,PR297 1.15K_0603_1% 3. Pop PH5 4.7K thermal resistor THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size Document Number R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS B MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 星期五 , 四月 25, 2003
SCHEMATIC, M/B LA-1452 R ev
1B
401230
A
B
C
D
E
F
G
Sheet
40 H
of
47
5
4
3
2
1
Version change list (P.I.R. List) Item
D
C
Fixed Issue
Page 1 of 1
Reason for change
Rev.
PG#
B.Ver#
Phase
1
Fireware issue
The ICH4 GNTA# strap pull up for EC BIOS
0.1A
18
Depop R153, GNTA# have internal pull up
0.1
SST
2
Leakage current issue
Reduce Broadcom 4401L leakage current
0.1A
22
Depop L39 and pop L7, conncetor power source from +3VALW to +3V, R31, R32, R33 pull up to +3VAUXLAN, Q3,Q4,Q5 pin3 connect to +3VAUXLAN
0.1
SST
3
Fix schematics part value
L21, L22, L23, L26 part value different with BOM
0.1B
15
Change L21, L22, L23, L26 part value from CHB2012U121 to BLM21A601SPT on schematics
0.1
SST
4
BOM issue
R445 include wrong part number
0.1B
33
Change R445 part number from SD028470200 to SD028680200. PN indicate value from 47K_0402_5% to 68K_0402_5%
0.1
SST
5
HDD leakage current issue
When AC in +5VSHDD will go up to 5V
0.1C
21
Q6 change to SI2302DS as schematics, SIDEPWR active low when HDD power on
0.1
SST
6
Capture library package issue
2N7002 Drain is pin1, Source is pin3
0.1C
28
Fixed Q30, Q31, Q32 Capture libaray , pin1 fixed to pin3, pin3 fixed to pin1
0.1
SST
7
BOM issue
Fixed R196~R199 from 56.2K ohm to 56.2 ohm
0.1C
23
Change R196~R199 PN from SD014562207 to SD014562A00 on schematics
0.1
SST
8
Fix LOM EEPROM issue
U8 (AT93C46) is used X16 organization
0.1C
22
NC or pop R452 to pull up U8 pin6 for X16 organization select
0.1
SST
9
Fix CLKRUN# leakage issue
ICH4 not implement CLKRUN#, GPIO24 is resume power well.
0.1D
19
Add a diode D46 to isolate GPIO24 from ICH4 to PCI devices, and depop D46.
0.2
PT
10
LOM EEPROM issue
U8 (AT93C46) is used X16 organization. U8 pin6 pull up or NC for X16 organization select, pull down for X8 organization selcet.
0.1D
22
U8 pin6 pull up +3VAUXLAN via R452 , and depop R452.
0.2
PT
11
SW BD LED keep turn on
SW BD LED control transistor Emitter conncet to +5VALW be keep LED always turn on
0.1D
32
Change JP5 pin9 from +5VS to +3VS
0.2
PT
12
Fix VCCA_SM voltage drop issue
Add current rating for VCCA_SM, VCCA_DPLL, VCCA_FSB (1.5VS)
0.1E
10
Change L3, L4, L27, L28 from MLF2012DR68XT to FBM-L11-201209- 0.2 121LMA05
PT
13
Change address and control signals layout topology
Change ddr address and control signal layout topology
0.1E
12,13
DDR address and control signals layout topology same the ddr data layout topology
0.2
PT
14
Fix EE issue item 89
Signal COMP/B and Y/G connect error
0.1E
17
Swap COMP/B and Y/G to correct connection
0.2
PT
15
Fix EE issue item 91
BEEP# from EC should be high active
0.1E
28
Change net name BEEP# to BEEP
0.2
PT
16
Fix EE issue item 92
Fix FSB 400MHz when 845GL pop
0.1E
15
Add R455 (8.2K_5%) pull down for H_BSEL0
0.2
PT
17
Fix EE issue item 95
When AC insertion SUSP# may be floating before the KBC can programit.
0.1E
33
Add R456 (100K_5%) pull down SUSP#
0.2
PT
18
Fix EE issue item 47
Provide enough current rating
0.1F
15
L22 and L26 change frome BLM21A601SPT (300mA) to FBM-L11-201209-121LMA05 (500mA) and depop L22
0.2
PT
19
Card Bus power bead current rating not enough
Provide enough current rating
0.1F
24
L5 and L6 change frome FBM-11-160808-800LMT_0603 (300mA) to FBM-L11-201209-121LMA05 (500mA)
0.2
PT
20
Fix EE issue item 102
Fix Intel CPU FSB frequency issue
0.1F
10,15
H_SEL0 connect to R270 pin1 from CLK generator, HBSEL0 connector to R270 pin2 from CPU. Depop R270 on GL board.
0.2
PT
21
Battery charge issue
ACIN pull up +3VALW can't change power supplier to battery when AC exit
0.1F
18
Depop R161
0.2
PT
B
A
Modify List
22
NO
Change PCMCIA connector
0.1F
24
Change PCMCIA conncetor from AMP_0-1376275-1 to JAE_JC21-BRB
0.2
PT
Fix INTRUDER issue
ESD protect for Q22
0.1F
32
Add C638, C639 for Q22 protection
0.2
PT
24
Remove PS2 connector
No necessary
0.1G
29
Remove RP7, JP26
0.2
PT
25
Add debug port
GL board have not pop minipci connector, we need a port 80 debug tool
0.1G
33
Add R458, C637 and JP27
0.2
PT
27
For cost save
For cost save
0.1G
32
Depop C10, C229 (150U Poly Cap), add C641, C642 (100U Petit Cap)
0.2
PT
28
It no need
Use R19 pop and depop to control H_SEL0 high or low
0.1G
15
Remove R455
0.2
PT
29
Fix EE issue item 134
Change ddr address and control signal layout topology
0.1H
12,13
Change DDR address and control signal to go back SST topology
0.2
PT
30
Fix EE issue item 149
Pop Petit Cap after EA test
0.1H
32
Depop C641,
0.2
PT
31
Fix EMI issue
EMI team's recommendation
0.1I
10
Pop R52, C79 for CLK_CLK_PCI_LAN; R428, C614 for CLK_PCI_MINI; R406, C597 for CLK_PCI_LPC; R321, C395 for CLK_ICH_66M
0.2
PT
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: 5
4
3
2
C
B
23
C642 and pop C10, C229
D
A
Compal Electronics, Inc. SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 ¬P 期五, 四月 25, 2003
Sheet 1
41
of
47
5
4
3
2
1
Version change list (P.I.R. List) Item
D
Page 1 of 1
Fixed Issue
Reason for change
Rev.
PG#
32
No
Connect MiniPci conncetor metal door to short to GND
0.1I
33
No
Some text mode use wire, change to line
0.1I
34
Fix power on issue
Use PCIRST# to set the SHDN_1632# work after PCIRST# high when power on
0.1I
6
Add Q62 gate connect to PCIRST#, source connect to SHDN_1632#
35
No
Change to use approve part
0.1I
31
RP118 (8.2K +-5% 4P2R) change to R453, R454 (8.2K_0402_5%)
26 10,30,40
Modify List
B.Ver#
Phase
0.2
PT
0.2
PT
0.2
PT
0.2
PT
0.2
PT
0.2
PT
0.2
PT
0.2
PT
Pop R234, C249 for CLK_MCH_DISPLAY; R286, C333 for CLK_MCH_66M
0.2
PT
Pop L1, L2, L15 Change form FCM-2012C-800 to FBM-10-201209-260T for PE board
0.2
PT
0.2
PT
0.2
PT
Add JP24 pin 127, 128 on schematics short to GND, JP24 footprint pin 127, 128 (metal lock door) be short to GND Some text mode use wire, change to line
D
36
No
Hard Disk source power change to +5VS
0.1I
21
Q6 change back to SI2301DS (PMOS) pin3 connect to +5VS
37
Fix EE issue item 134
Change DDR address and control signal topology back to REV0.1
0.1I
12,13
Change DDR address and control signal topology back to REV0.1
38
Fix EE issue item 171
For CRT Hsync and Vsync to allow tuning
0.1I
17
Add series resistors R459, R460 for Hsync and Vsync
39
No
Schematic version change for PT build
0.2
ALL
Change revision from 0.1I to 0.2
40
Fix issue item 20
41
Fix CRT rising and falling time issue
42
No
43
No
Slow rising and falling time
0.2A
10
0.2A 17
Fast rising and falling time 0.2A Change Board ID output level
Pop R393 100K_0603_1% for Board ID 30
C
C
0.2A 24
Add off-page reference 44
Add off-page on pg24 PCMCIA connector
No
0.2B
ALL
Modify Text 0.2A
PT-2
0.2C
21
Add C643 22U_1206 replace C387's layout location and C387 leave DIMM area.
0.2A
PT-2
0.2C
24 JP18 pin75,76,77,78,79,80,81,82 connect to GND
0.2A
PT-2
Remove PM_GMUXSEL signal net
0.2A
PT-2
0.2A
PT-2
0.2A
PT-2
0.2A
PT-2
0.2A
PT-2
Net in for Rev 0.2A Gerber 45
Fix DFX issue
46
No
47
No
PM_GMUXSEL for mobil platform to support SpeedStep, desktop platform just GPIO fuction
0.2C
19
48
Fix PIR2 issue
PIR not match schemaitcs
0.2F
22
C387 effect DIMM door lock Add JP18 PCMCIA connector GND pads
B
Pop L39 and depop L7
49
Fix PIR19 issue
PIR not match schemaitcs
0.2F
24
L5, L6 change to FBM-L11-201209-221LMAT (3A). And Depop L5
50
Fix PIR23 issue
PIR not match schemaitcs
0.2F
32
Depop C638
51
Fix PIR24 issue
PIR not match schemaitcs
0.2F
30
RP7 pop for pull up PS2 signal
52
Fix PIR25 issue
PIR not match schemaitcs
0.2F
33
JP27 pop on GL board for debug and depop on PE board 0.2A
PT-2
53
Fix EE issue item 62
Schematics component's PN not match BOM
0.2G
29
JP13 (TP CONN) PN change to "SP020010910" in schematics to match BOM
0.2A
PT-2
54
Fix EE issue item 63
Schematics component's PN not match BOM
0.2G
29
JP25 (MDC CONN) PN change to "SP02F00410L" in schematics to match BOM
0.2A
PT-2
55
Fix EE issue item 64
Schematics component's PN not match BOM
0.2G
32
JP4 (USB CONN) PN change to "DC23310241L" in schematics to match BOM
0.2A
PT-2
56
3VDDCDA, 3VDDCCK rising time issue
3VDDCDA, 3VDDCCK rising slow on SMBus EA measurement
0.2G
17
R5, R201 change from 10K_0402_5% to 2K_0402_5%
0.3
ST
57
EE issue list item 91
CLK_PCI_ICH timing out of spec
0.2H
18
Pop R349 (22_0402_5%), C480 (10P_0402_50V8K) for CLK_PCI_ICH AC termination
0.3
ST
58
EE issue list item 103
Depop sub thermal sensors for cost save
0.2H
8
Depop U25, U23, C394, C482, R308, R351 and R306
0.3
ST
59
Fix Boardcom 4401L wake up from S3 issue
Fix Boardcom 4401L wake up from S3 issue
0.2H
22
Add R461, R462 and depop R462. Option VESD and VDDBUS power source from +3VS to +3VAUXLAN. C97, C96, C77, C74, C88, C87, C80 bypass +3VWOL
0.3
ST
60
EE issue list item 103
H_BSEL0 of 845PE should get 1.5V at input and CLK chip should be seeing 3.3V with 533MHz CPU
0.2H
15
Add R463 (0_0402_5%) Pop on PE board. R19 move to CPU side and power source +3VS.
0.3
ST
B
A
A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: 5
4
3
2
Compal Electronics, Inc. SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 ¬P 期五, 四月 25, 2003
Sheet 1
42
of
47
5
4
3
2
1
Version change list (P.I.R. List) Item
Page 1 of 1
Fixed Issue
Reason for change
Rev.
PG#
61
ESD protection on 2nd FAN
ESD protection on 2nd FAN
0.2I
7
62
Fix EE issue item 105
H_BSEL0 circuit not correct
0.2I
63
No
Change Board ID for ST build
0.2I
30
64
No
Change for ITP test on PCBA
0.2I
6, 8
65
Fix EE issue item 126
0.2J
66
RJ11 ISN failed
EMI team recommend to resolve RJ11 ISN test failed
0.2J
67
Fix EE issue item 140
Connect 9C/12C#/8C# to EC GPIO for future 9Cell support if required
0.2K
68
TI TPS793475DBVR damage issue
When power on, there are 1.5A sink current when TPS793475DBVR started
0.2K
69
Fix EE issue item 136
0.2K
Modify List
B.Ver#
Phase
Reserve Q63 (SM05) for 2nd FAN ESD protection
0.3
ST
Serie resistor R270 for CPU and MCH
0.3
ST
R394 change from 10K_0603_1% to 24.9K_0603_1%
0.3
ST
Depop R313, R305 and pop R310, R372, R183, R184, R304
0.3
ST
22
C211, C212 change package from 1206 size to 1808.
0.3
ST
29
Cut a seperated GND for MDC and connect to system GND via a schottky diode. Reserve a jump for connect system and MDC GND.
0.3
ST
Connect 9C/12C#/8C# from PR162 to U30 pin17 and remove R388
0.3
ST
29
For power solution, C558 change package size from 0402 to 0603 for value tolerance
0.3
ST
6
R311 change to 4.7K_0402_5%, H_PROCHOT# connect to PD36
0.3
ST
D
D
C
70
B
Fix ThermTrip function
Using larger cap for high-pot margin
Add hardware circuit to sense Adapter current and automatically generate PROCHOT to the CPU to generate automatic throttling
10, 15
31, 34
C
When thermal protective resistor PH1 work, SHDN_1632# can't tie to low
0.2K
6
R320 connect to Q59 base, R316 connect to Q59 collector and VL power source. Add Q64 between Q59 and Q62. Q62 change pin1 Drain to connect SHDN_1632#
0.3
ST
71
RJ11 ISN failed
Change solution for ISN failed
0.3
29
Remove PJP9-13 and D47
0.3
ST
72
Fix EE issue item 136
Follow Intel desing guide recommend pull up resistor value
0.3
6
R311 change back to 62_0402_5%
0.3
ST
73
Fix EE issue item 141
Prevent noise issue
0.3
28
Depop R328 for noise prevention
0.3
ST
74
No
For cost save
0.3
7
Depop C148, C150 (470U_D4_2.5VM) and C152 (330U_D2E_2.5VM)
0.3
ST
75
Fix PROTO3 EE issue item 44
Minipci connector pop for PE board only
0.3B
26
Add 2@ symbol for JP24 for PE board pop only
0.3
ST
76
No
Vendor schematics review recommendation
0.3B
22
R35 change from 10K_0402_5% to 1K_0402_5%
0.3
ST ST
Fix PROTO3 EE issue item 45
Remove minipci suport component for GL board cost save
0.3B
26
Remove R405, R399, C600, C596, C613, C612, C599, C598, C609, L35, C616, C610, L36, R401, R403 on GL board
0.3
77
78
No
Modify material value
0.3C
Change value L11,L30,L31,L35,L36 from BDM21A05 _0805 to BLM21A05 _0805
0.3
ST
79
No
Modify material part number
0.3C
27
U24 STAC9750 change from (SA097500000) to (SA097500010) for both BOM
0.3
ST
80
No
0.3C
7
Delete R11,D11,D20,U1,R10,R6,Q1,C234,Q8,JP19
0.3
ST
23,26, 27,28
B
Depop Fan2 Control circuit 79
No
EMI require
1.0
17
Pop D1, D3, D18 for EMI requirement
1.0
QT
80
No
Modify Fiduial Mark & Screw Hole value for non pop
1.0
29
Fiduial Mark & Screw Hole value add @ symbol
1.0
QT
81
No
BD_ID change for QT build
1A
30
R394 change from 24.9K_0603_1% to 43K_0603_1%
1.0
QT
A
A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: 5
4
3
2
Compal Electronics, Inc. SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 ¬P 期五, 四月 25, 2003
Sheet 1
43
of
47
5
4
3
2
1
Version change list (P.I.R. List) Item
Page 1 of 1
Fixed Issue
Reason for change
Rev.
PG#
82
INTRUDER# issue
Sometimes when normal shutdown, INTRUDER# record a event
1A
32
83
No
Because Q22 change to DTC115EKA, C639 is no necessory
1B
Modify List
B.Ver#
Phase
Q22 change from 2N7002 to BJT DTC115EKA
1.0
QT
32
Depop C639 (1000P_0402_50V7K)
1.0
QT
1B
29
The serie resistor R441 change from 22_0402_5% to 10_0402_5%
1.0
Pilot
1C
28
Depop C580 and change C588 from 4.7uf to 0.47uf
1.0
RTS
D
D
84
Fix Qual issue item 35
85
Fix audio not switching to headphones or ext speakers immediately
Improve IAC_SDATA_IN1 singnal quaility For audio switching to headphones or ext speakers immediately
C
C
B
B
A
A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: 5
4
3
2
Compal Electronics, Inc. SCHEMATIC, M/B LA-1452 Document Number
R ev 1B
401230 ¬P 期五, 四月 25, 2003
Sheet 1
44
of
47
5
4
3
2
Version change list (P.I.R. List) Item D
1
Fixed Issue
Rev.
PG#
Pin7 of PU16 can't be used as on/off control pin
0.1B
40
1. Change VCC power source of PU16 from +5VALWP to +5VS
0.1
SST
Current limtited is about 37A while PH6,PH7,PH8 is 1.5K that is not enough for design target.Because we don't use PTC resistor on PCB now, the value must be tuned later.
0.1B
40
1. Change PH6,PH7,PH8 from 1.5K_0603_5% to 3K_0603_1%
0.1
SST
Vgs of PQ19 is 2V while PR72 is 47K. That is not enough. While PR72 is 22K, the Vgs can be improved to 2.5V.
1. Change PR72 from 47K_0402_5% to 22K_0402_5%
0.1
SST
0.1B
35
FBM-L11-322513-151LMAT is 5A that is not enough.So FBM -L18-453215-900LMA90T1812 is 9A that is better.
PT
35
1. Change PL8 from FBM-L11-322513-151LMAT to FBM -L18-453215-900LMA90T1812.
0.2
0.1B
On SST PCB, we can sound some noise due to PC77, the cernamic capacitor has sounded noise with thinner type.
0.1C
36
1. Change PC77 from 2.2U_1206_25V to 4.7U_1210_25V
0.2
PT
The transient response is too slow. We must to tune feedback resistor and capacitor to fix it.
0.1E
40
1. Change PR249 from 3.48K_0603_1% to 5.76K_0603_1%. 2. Change PR257 from 49.9_0603_1% to 1.1K_0603_1% 3. Populate PC172 68PF_0603_50V.
0.2
PT
Add bypass capacitor pallel
0.1E
38
Populate PC218 470P_0603_50V7K
0.2
PT
Add pulldown resistor tie to GND while VR_ON is float that can be made sure the logic is low.
0.2
PT
0.1E
40
Add PR301 100K_0603_1%
Negative voltage was observed on +5VALWP when system powered off
0.1E
40
0.2
PT
ISL6219 caused OVP when on/off pin changed from high to low level
0.1E
40
0.2
PT
Fine-tune current sharing of CPU VR phase1,2,3 to have thermal balance
uneven current sharing found
0.1E
0.2
PT
Fine-tune CPU load-line with NTC
Fine-tune CPU load-line with NTC
CPU_CORE can't
power up
current limited is not
3
Turn on voltage of PQ19 is not eonugh
5
up to 60A
current rating is not enough.
Fix noise issue
6 Fix
C
CPU_CORE Transient Response fail
7
SDREF output voltage is over spec.
8
PG of CM28423 has a glitch while VCC is ready and VR_ON is float
9
10
Page 1 of 3
Reason for change
2
4
1
Change VCC power source of PU15, PU17, PU19 from +5VALWP to +5VS Prevent abnoral function OVP caused by ISL6219 while system powerwd off ; bouble pulses was observed at output PW1, PW2, PWM3 of ISL6219
pin18 of ISL6225
Modify List
B.Ver#
1. Change VCC power source of PU15, PU17, PU19 from +5VALWP to +5VS 1. Add PQ82 2N7002 2. Change PR232 from 5.1_0603_5% to 10K_0603_5% 3. Change PC168 from 1U_0805_25V to 0.01U_0603_50V. 4. Depop PR251, PR270, PC183, PC194 5. Tie the EN pin of PU15, PU17, PU19 to Pin1 of PQ82
Phase D
C
11
B
12
13
0.1E
Audio noise found Still find root cause
0.1E
40
40
35, 36, 38, 40
14
PC212 location space change
requested by ME to put a connector around
0.1E
38
15
Remove
no possibilty to have a reverse voltage at Vin when adapter plug-in because of the DC-jack orientation structure
0.2C
34
16
Prevent PU14 from burn out
1. 2. 3. 4.
Change Change Change Change
PH6, PH7, PH8 form 3K_0603_1% to 0_0603_5% PR245 from 0_0603_5% to 1.96K_0603_1% PR263 from 0_0603_5% to 1.43K_0603_1%. PR276 from 0_0603_5% to 1.5K_0603_1%
1. 2. 3. 4. 5. 6. 7. 8. 7. 8.
Keep PR268 nonpop Change PR256 from 2K_0603_1% to 1.74K_0603_1% Change PR297 from 0_0603_5% to 1.15K_0603_1%. Change PH5from depop to 4.7K_0603_1% Change PR298 from depop to 681_0603_1% Change PR257 from 49.9_0603_1% to 909_0603_1% Change PC179 from 3900P_0603_50V to 5.6N_0603_50V Change PR249 from 3.48K_0603_5% to 7.5K_0603_1% Change PC171 from 6800P_0603_50V to 5.6N_0603_50V Change PC172 from depop to 47P_0603_50V
B
0.2
PT
1. reserve 15U_D_25V capacitors on PC226-PC235,
0.2
PT
1. change the size of PC212 from D size to 0805 and pop 4.7U_0805_10V
0.2
PT
0.2A
PT-2
0.2A
PT-2
1.delete PD5 from schematics PD5
A
A
When pin1 (GND pin) of DC-jack PCN1 disconnected from B/M (damaged by force from outside), there is a large current going through PU14 resulted in PU14 damaged
0.2C
39
Add PR302 10K_0603_5%
Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5
4
3
2
SCHEMATIC, M/B LA-1452 Document Number
Rev 1B
401230 星期五, 四月 25, 2003
Sheet 1
45
of
47
5
4
3
2
Version change list (P.I.R. List) Item D
C
17
Fixed Issue 100MHz EMI broad-band over spec.
Page 2 of 3
Reason for change Improve 100MHz EMI broad-band
Rev.
PG#
0.2E
34
18
100MHz EMI broad-band over spec.
Improve 100MHz EMI broad-band
0.2H
34
19
Precharge function has some bug, while AC Adapter plug in firt time
Precharge can reduce surge current from AC adapter,while Adapter plugged in
0.2H
34
20
Power rating of 0.02_2010 is not enough.
21
Power open issue
22
Power good giltch issue in ISL6225
23
1
rating power of 0.02_2010 is 0.5W that is very poor for 90W adpater
Modify List
B.Ver#
Add a FBM-L18-453215-900-LMA90T_1812 bead on PL7
1. Change PL6,PL7 from FBM-L18-453215-900-LMA90T_1812 to MCK4532800YAT_1812 2. Add PL4 MBH2012102YZT_0805 3. Change PC45 from 100P to 560P, PC46 from 1000P to 12P,PC47 from 100P to 12P and PC48 from 1000P to 560P
1. Change PR51 from 1M to 2.2M,PR55 from 215K to 191K. 2. Change PR54 from 10K to 34K,add PR32 66.5K. 3. Change PC51 from 0.1U_16V to 1000P_50V. 4. Change PC50 from 1000P_50V to 0.1U_16V. 5. Change net +5VP and RTCVREF to VL. 6. Change PR113 from 47K_0402_5% to 0_0402_5%. 7. De-pop PC111 and change PC158 from 0.1U_16V to 0.47U_16V.
Phase
0.2A
PT-2
0.3
ST
0.3
ST
0.2H
35
1. Change PR65 from 0.02_2010_1% to 0.02_2512_1%.
0.3
ST
0.2H
36
Change PH1
0.3
ST
The giltch occurs while secondary PWM is enabled that effects system boots up
0.2H
38
1. Add PR31 1K_0402_5%.. 2. De-pop PR294
0.3
ST
Fix open issue #137
DELL don't aprove item22 solution, prefer using new version ISL6225
0.2J
38
1. De-pop PR31 1K_0402_5%. 2. De-pop PR294 0_0402_5%. 3. Add PR30 0_0402_5%.
0.3
ST
24
Fix open issue #124
Fix open issue #124 and using ISL6219A
0.2J
40
0.3
ST
25
Fix ISN fail issue
Fix ISN fail with 200KHz
0.2J
35
1. Change PR81 from 66.5K_0603_1% to 47K_0603_1% 2. Change PC55 and PC56 from 4.7U_1210_25V to 10U_1210_25V 3. Change PL9 from 15UH to 22UH
0.3
ST
Change PQ14,PQ15,and PQ16 from SI4835DY to SI4825DY
0.3
ST
0.3
ST
0.3
ST
D
C
Change size of thermal resistor and cost down
B
26
Fix open issue #123
Rds(on) of SI4835DY is too high,change PQ14,15,16 to SI4825DY for power stress
27
Adapter shut down while running P4MaxPower 100%
Adapter current over 5.5A 4 sec while running P4MaxPower 100%
28
Modify thermal protect temp. from 95C to 87C
Based on thermal team requirement
0.2J
35
0.3
37
0.3A
36
1. 2. 3. 4.
from 10K_0805_1% to 10K_0603_1%.
Change PR232 from 10K_0603_5% to 5.1_0603_5%. Populate PR251 and PR270 5.1_0603_5% Populate PC183 and PC194 0.01U_0603_50V. De-pop PQ82,PD31,PD,32
1. add PR303, PR306 47K_0402_1%. 2. add PR304 1M_0402_1%. 3. add PR305 226K_0402_1% 4. add PR307 147K_0402_1% 5. add PR308 100K_0402_1% 6. add PC236 0.01U_0603_50V 7. add PC239 0.1U_0603_16V 8. add PC238 1000P_0402_50V 9. add PQ83, PQ84 2N7002 10. add PU21 LM393A
1. ChangePR119 from 21K_0603_1% to 17.8K_0603_1% 2. Change PR117 from 1.74K_0603_1% to 2.05K_0603_1%
B
A
A
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5
4
3
2
SCHEMATIC, M/B LA-1452 Document Number
Rev 1B
401230 星期五, 四月 25, 2003
Sheet 1
46
of
47
5
4
3
2
Version change list (P.I.R. List) Item
Fixed Issue
Page 3 of 3
Reason for change
Rev.
PG#
D
29
modify compension for reduce output capacitor
30
Fix item25 about ISN test without changing inductor
31
Capacitor DFX issues
32
Noise issue in B+ power
1
modify compension for reduce output capacitor
0.3A
40
Fix item25 about ISN test without changing inductor
0.3A
35
Component layout pad overlap (reservated for noise issue) causes some components shifting when pass the re-flow
0.3D
Add reservated caps. back for noise issue
0.3E
35
36
38
40
35
36
38
40
Modify List 1. 2. 3. 4.
De-pop Change Change Change
PR257 PC171 PC172 PR249
B.Ver#
and PC179. from 5.6N_0603_50V to 15N_0603_50V form 47P_0603_50V to 150P_0603_50V from 7.5K_0603_1% to 10K_0603_1%
Phase D
0.3
ST
1. Change PL9 from 22UH_SPC-1205P-220A to 15UH_SPC-1204P-150
0.3
ST
remove PC226, PC227, PC228, PC229, PC230, PC231, PC232, PC233, PC234, PC235
1.0
QT
1.0
QT
1.0
QT
1.0
QT
reserve PC226, PC227, PC228, PC229, PC230, PC231, PC232, PC233, PC234, PC235
C
C
1. Change PR117 from 2.05K_0603_1% to 1.96K_0603_1% 2. Change PR119 from 17.8K_0603_1% to 19.1K_0603_1%
33
Change OTP from 87C to 90C
Change OTP from 87C to 90C
1.0B
36
34
Fine tune adaptor detector
Fine tune adaptor detector
1.0B
37
35
Use new version ISL6225
Use new version ISL6225
1.0B
38
1. Change PU20 from ISL6225CA to ISL6225BCA
1.0
QT
36
Fix surge voltage in +CPU_CORE while power up
Fix surge voltage in +CPU_CORE while power up
1.0B
40
1. 2. 3. 4.
1.0
QT
1. 2. 3. 4.
Change Change Change Change
PC238 PC239 PR304 PR307
from from from from
1000P_0603_50V% to 0.022U_0402_16V 0.1U_0603_16V to 0.01U_0603_50V 1M_0402_1% to 2M_0402_5% 147K_0402_1% to 137K_0402_1%
Add PR244,PR262,PR277 499K_0603_1% No populate PR251,PR270,PC183 and PC194. Change PR232 from 5.1_0603_5% to 10K_0603_5%. Add PQ82 2N7002
B
B
A
A
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5
4
3
2
SCHEMATIC, M/B LA-1452 Document Number
Rev 1B
401230 星期五, 四月 25, 2003
Sheet 1
47
of
47
